6 Pin Configuration and Functions

Figure 6-1 BQ25895RTW (WQFN)Top View

Table 6-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	TYPE⁽¹⁾	DESCRIPTION
VBUS	1	P	Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1-µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC.
D+	2	AIO	Positive line of the USB data line pair. D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and Adjustable high voltage adapter (MaxCharge).
D–	3	AIO	Negative line of the USB data line pair. D+/D- based USB host/charging port detection. The detection includes data contact detection (DCD), primary and secondary detection in BC1.2, and Adjustable high voltage adapter (MaxCharge).
STAT	4	DO	Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10-kΩ resistor. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin blinks in 1 Hz. The STAT pin function can be disabled when STAT_DIS bit is set.
SCL	5	DI	I²C Interface clock. Connect SCL to the logic rail through a 10-kΩ resistor.
SDA		DIO	I²C Interface data. Connect SDA to the logic rail through a 10-kΩ resistor.
INT	7	DO	Open-drain Interrupt Output. Connect the INT to a logic rail via 10-kΩ resistor. The INT pin sends active low, 256-µs pulse to host to report charger device status and fault.
OTG	8	DI	Boost mode enable pin. The boost mode is activated when OTG_CONFIG =1, OTG pin is high, and no input source is detected at VBUS
CE	9	DI	Active low Charge Enable pin. Battery charging is enabled when CHG_CONFIG = 1 and CE pin = Low. CE pin must be pulled High or Low.
ILIM	10	AI	Input current limit Input. ILIM pin sets the maximum input current and can be used to monitor input current ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 0.8 V. A resistor is connected from ILIM pin to ground to set the maximum limit as I_INMAX = K_ILIM/R_ILIM. The actual input current limit is the lower limit set by ILIM pin (when EN_ILIM bit is high) or IIINLIM register bits. Input current limit of less than 500 mA is not support on ILIM pin. ILIM pin can also be used to monitor input current when the voltage is below 0.8V. The input current is proportional to the voltage on ILIM pin and can be calculated by I_IN = (K_ILIM x V_ILIM) / (R_ILIM x 0.8) The ILIM pin function can be disabled when EN_ILIM bit is 0.
TS	11	AI	Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to GND. Charge suspends when either TS pin is out of range. Recommend 103AT-2 thermistor.
QON	12	DI	BATFET enable/reset control input. When BATFET is in ship mode, a logic low of t_SHIPMODE duration turns on BATFET to exit shipping mode. When VBUS is not plugged-in, a logic low of t_{QON_RST} duration resets SYS (system power) by turning BATFET off for t_{BATFET_RST} and then re-enable BATFET to provide full system power reset. The pin contains an internal pull-up to maintain default high logic
BAT	13,14	P	Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin.
SYS	15,16	P	System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. Connect a 20uF closely to the SYS pin.
PGND	17,18	P	Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin.
SW	19,20	P	Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047µF bootstrap capacitor from SW to BTST.
BTST	21	P	PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047µF bootstrap capacitor from SW to BTST.
REGN	22	P	PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7µF (10 V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin.
PMID	23	DO	Battery boost mode output. Connected to the drain of the reverse blocking MOSFET (RBFET) and the drain of HSFET. If OTG is not used, the minimum capacitance required on PMID to PGND is 8.2 μF. If OTG is used, the minimum capacitance required on PMID to PGND is 40 μF for up-to 2.4A output and 60 μF for up-to 3.1A output.
DSEL	24	DO	Open-drain D+/D- multiplexer selection control. Connect the DSEL to a logic rail via 10-KΩ resistor. The pin is normally float and pull-up by external resistor. During Section 8.2.3.3, the pin drives low to indicate the device D+/D- detection is in progress and needs to take control of D+, D- signals. When detection is completed, the pin keeps low when MaxCharge is detected. The pin returns to float and pulls high by external resistor when other input source type is detected.
PowerPAD™		P	Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD Pad to the board, and have vias on the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter.

(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)