ZHCSDI5C March 2015 – October 2022 BQ25895
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | RW |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description | |
|---|---|---|---|---|---|
| 7 | BAT_LOADEN | R/W | by REG_RST by Watchdog | Battery Load (IBATLOAD) Enable 0 – Disabled (default) 1 – Enabled | |
| 6 | WD_RST | R/W | by REG_RST by Watchdog | I2C Watchdog Timer Reset 0 – Normal (default) 1 – Reset (Back to 0 after timer reset) | |
| 5 | OTG_CONFIG | R/W | by REG_RST by Watchdog | Boost (OTG) Mode Configuration 0 – OTG Disable 1 – OTG Enable (default) | |
| 4 | CHG_CONFIG | R/W | by REG_RST by Watchdog | Charge Enable Configuration 0 - Charge Disable 1- Charge Enable (default) | |
| 3 | SYS_MIN[2] | R/W | by REG_RST | 0.4V | Minimum System Voltage Limit Offset: 3.0V Range 3.0V-3.7V Default: 3.5V (101) |
| 2 | SYS_MIN[1] | R/W | by REG_RST | 0.2V | |
| 1 | SYS_MIN[02] | R/W | by REG_RST | 0.1V | |
| 0 | Reserved | R/W | by REG_RST by Watchdog | Reserved (default = 0) | |