ZHCSRB7A December 2022 – October 2023 BQ27427
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Supply Current
- 5.6 Digital Input and Output DC Characteristics
- 5.7 LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics
- 5.8 LDO Regulator, Wake-up, and Auto-Shutdown AC Characteristics
- 5.9 ADC (Temperature and Cell Measurement) Characteristics
- 5.10 Integrating ADC (Coulomb Counter) Characteristics
- 5.11 Integrated Sense Resistor Characteristics, –40°C to 85 °C
- 5.12 I2C-Compatible Interface Communication Timing Characteristics
- 5.13 SHUTDOWN and WAKE-UP Timing
- 5.14 Typical Characteristics
- 6 Detailed Description
- 7 Application and Implementation
- 8 Power Supply Recommendation
- 9 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
5.12 I2C-Compatible Interface Communication Timing Characteristics
TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| Standard Mode (100 kHz) | ||||||
| td(STA) | Start to first falling edge of SCL | 4 | μs | |||
| tw(L) | SCL pulse duration (low) | 4.7 | μs | |||
| tw(H) | SCL pulse duration (high) | 4 | μs | |||
| tsu(STA) | Setup for repeated start | 4.7 | μs | |||
| tsu(DAT) | Data setup time | Host drives SDA | 250 | ns | ||
| th(DAT) | Data hold time | Host drives SDA | 0 | ns | ||
| tsu(STOP) | Setup time for stop | 4 | μs | |||
| t(BUF) | Bus free time between stop and start | Includes Command Waiting Time | 66 | μs | ||
| tf | SCL or SDA fall time(1) | 300 | ns | |||
| tr | SCL or SDA rise time(1) | 300 | ns | |||
| fSCL | Clock frequency(2) | 100 | kHz | |||
| Fast Mode (400 kHz) | ||||||
| td(STA) | Start to first falling edge of SCL | 600 | ns | |||
| tw(L) | SCL pulse duration (low) | 1300 | ns | |||
| tw(H) | SCL pulse duration (high) | 600 | ns | |||
| tsu(STA) | Setup for repeated start | 600 | ns | |||
| tsu(DAT) | Data setup time | Host drives SDA | 100 | ns | ||
| th(DAT) | Data hold time | Host drives SDA | 0 | ns | ||
| tsu(STOP) | Setup time for stop | 600 | ns | |||
| t(BUF) | Bus free time between stop and start | Includes Command Waiting Time | 66 | μs | ||
| tf | SCL or SDA fall time(1) | 300 | ns | |||
| tr | SCL or SDA rise time(1) | 300 | ns | |||
| fSCL | Clock frequency(2) | 400 | kHz | |||
(1) Specified by design. Not production tested.
(2) If the clock frequency (fSCL) is > 100 kHz, use 1-byte write
commands for proper operation. All other transactions types are supported at 400
kHz. (See Section 6.3.1.1 and Section 6.3.1.3.)
Figure 5-1 I2C-Compatible Interface Timing Diagrams