8.3.5.7.3 I²C Clock Stretching

I²C clock stretches can occur during all modes of fuel gauge operation. In the SLEEP and HIBERNATE modes, a short clock stretch will occur on all I²C traffic as the device must wake-up to process the packet. In NORMAL and SLEEP modes, clock stretching will only occur for packets addressed for the fuel gauge. The timing of stretches will vary as interactions between the communicating host and the gauge are asynchronous. The I²C clock stretches may occur after start bits, the ACK/NAK bit, and first data bit transmit on a host read cycle. The majority of clock stretch periods are small (≤ 4 ms) as the I²C interface peripheral and CPU firmware perform normal data flow control. However, less frequent but more significant clock stretch periods may occur when data flash (DF) is being written by the CPU to update the resistance (Ra) tables and other DF parameters, such as Qmax. Due to the organization of DF, updates need to be written in data blocks consisting of multiple data bytes.

An Ra table update requires erasing a single page of DF, programming the updated Ra table and a flag. The potential I²C clock stretching time is 24-ms max. This includes 20-ms page erase and 2-ms row programming time (×2 rows). The Ra table updates occur during the discharge cycle and at up to 15 resistance grid points that occur during the discharge cycle.

A DF block write typically requires a max of 72 ms. This includes copying data to a temporary buffer and updating DF. This temporary buffer mechanism is used for protection from power failure during a DF update. The first part of the update requires 20 ms time to erase the copy buffer page, 6 ms to write the data into the copy buffer, and the program progress indicator (2 ms for each individual write). The second part of the update is writing to the DF and requires 44-ms DF block update time. This includes a 20-ms each page erase for two pages and a 2-ms each row write for two rows.

In the event that a previous DF write was interrupted by a power failure or reset during the DF write, an additional 44-ms max DF restore time is required to recover the data from a previously interrupted DF write. In this power failure recovery case, the total I²C clock stretching is 116-ms max.

Another case where I²C clock stretches is at the end of discharge. The update to the last discharge data will go through the DF block update twice because two pages are used for the data storage. The clock stretching in this case is 144-ms max. This occurs if there has been a Ra table update during the discharge.