ZHCSKS9B February 2020 – November 2022 BQ27Z561-R2
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VIH | High-level input voltage (assured by design) | VREG18 = 1.8 V | 0.75 × VBAT | V | ||
VIL | Low-level input voltage low (assured by design) | VREG18 = 1.8 V | 0.25 × VBAT | V |