ZHCSKS9B February 2020 – November 2022 BQ27Z561-R2
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
fSCL | Clock operating frequency | SCL duty cycle = 50% | 100 | kHz | ||
tHD:STA | Start condition hold time | 4.0 | µs | |||
tLOW | Low period of the SCL Clock | 4.7 | µs | |||
tHIGH | High period of the SCL Clock | 4.0 | µs | |||
tSU:STA | Setup repeated START | 4.7 | µs | |||
tHD:DAT | Data hold time (SDA input) | 0 | ns | |||
tSU:DAT | Data setup time (SDA input) | 250 | ns | |||
tr | Clock rise time | 10% to 90% | 1000 | ns | ||
tf | Clock fall time | 90% to 10% | 300 | ns | ||
tSU:STO | Setup time STOP condition | 4.0 | µs | |||
tBUF | Bus free time STOP to START | 4.7 | µs |