ZHCSDT5C September   2010  – March 2016

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Recommended Cell Balancing Configurations
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Protection
      2. 8.1.2 Cell Balancing
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Protection (OUT) Timing
      2. 8.3.2 Cell Voltage > VPROTECT
      3. 8.3.3 Cell Connection Sequence
      4. 8.3.4 Cell Balance Enable Control
      5. 8.3.5 Cell Balance Configuration
      6. 8.3.6 Cell Imbalance Auto-Detection (Via Cell Voltage)
      7. 8.3.7 Customer Test Mode
      8. 8.3.8 Test Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 PROTECTION Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Battery Connection
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
    3. 9.3 System Example
      1. 9.3.1 External Cell Balancing
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 Glossary
  13. 13机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • DRB|8
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 修订历史记录

Changes from B Revision (December 2014) to C Revision

  • Changed 典型应用标题至简化原理图 Go
  • Changed 电阻器 RVD 的位置，在简化原理图图形中添加了 PACK+ 和 PACK-Go
  • Deleted the Lead Temperature (soldering) from the Absolute Maximum Ratings table Go
  • Deleted table notes 2 through 7 from the Thermal InformationGo
  • Changed resistor RVD location in Figure 9 Go
  • Added title to Table 1Go
  • Changed resistor RVD location, added PACK+ and PACK- in Figure 11 Go

Changes from A Revision (September 2010) to B Revision

  • Added ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go

Changes from * Revision (June 2010) to A Revision

  • Changed values in XDELAY and XDELAY_CTM electrical characteristicsGo
  • Changed specifications for VOUTGo
  • Changed test conditions for VOUT, IOH, and IOLGo
  • Added VMM_DET_ON: VC2 = VDD = 7.6 VGo
  • Changed VMM_DET_OFF: From VDD – VC2 – 7.6 V to VC2 = VDD = 7.6 VGo
  • Changed content in Recommended Cell Balancing Configurations sectionGo
  • Added ICD Charge Current figureGo
  • Added ICD Discharge Current figureGo
  • Changed XDELAY from nominally 8.0 s/µF to nominally 9.0 s/µFGo
  • Changed Timing for Overvoltage Sensing figureGo
  • Added Cell Imbalance Auto-Detection (Via Cell Voltage) sectionGo
  • Changed VDD value in Customer Test Mode from 8.5 V to 9.5 VGo
  • Changed the Voltage Test Limits figureGo
  • Added External Cell Balancing sectionGo
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