The following tests are referenced as follows: The COUT and DOUT outputs are “H,” which are higher than the threshold voltage of the external logic level FETs and regarded as ON state. “L” is less than the turn ON threshold for external NMOS FETs and regarded as OFF state. The COUT pin is with respect to V–, and the DOUT pin is with respect to VSS.

1. Overcharge detection voltage and overcharge release voltage (Test Circuit 1):

   The overcharge detection voltage (V_OVP) is measured between the BAT and VSS pins, respectively. Once V1 is increased, the over-detection is triggered, and the delay timer expires. Then, COUT transitions from a high to low state and reduces the V1 voltage to check for the overcharge hysteresis parameter (V_OVP-Hys). The delta voltage between overcharge detection voltages (V_OVP) and the overcharge release occurs when the CHG FET drive output goes from low to high.

2. Over-discharge detection voltage and over-discharge release voltage (Test Circuit 2):

   Over-discharge detection (V_UVP) is defined as the voltage between BAT and VSS at which the DSG drive output goes from high to low by reducing the V1 voltage. V1 is set to 3.5V and gradually reduced while V2 is set to 0V. The over-discharge release voltage is defined as the voltage between BAT and VSS at which the DOUT drive output transition from low to high when V1 voltage is gradually increased from a V_UVP condition. The overcharge hysteresis voltage is defined as the delta voltage between V_UVP and the instance at which the DOUT output drive goes from low to high.

3. Discharge overcurrent detection voltage (Test Circuit 2):

   The discharge overcurrent detection voltage (V_OCD) is measured between V– and VSS pins and triggered when the V2 voltage is increased above V_OCD threshold with respect to VSS. This delta voltage once satisfied will trigger an internal timer t_OCDD before the DOUT output drive transitions from high to low.

4. Load short circuit detection voltage (Test Circuit 2):

   Load short-circuit detection voltage (V_SCC) is measured between V– and VSS pins and triggered when the V2 voltage is increased above V_SCC threshold with respect to VSS within 10µs. This delta voltage, once satisfied, triggers an internal timer t_SCCD before the DOUT output drive transitions from high to low.

5. Charge overcurrent detection voltage (Test Circuit 2):

   The charge overcurrent detection voltage (V_OCC) is measured between VSS and V– pins and triggered when the V2 voltage is increased above V_OCC threshold with respect to V–. This delta voltage, once satisfied, triggers an internal timer t_OCCD before the COUT output drive transitions from high to low.

6. Operating current consumption (Test Circuit 2):

   The operating current consumption I_BNORMAL is the current measured going into the BAT pin under the following conditions: V1 = 3.9V and V2 = 0V.

7. Power down current consumption (Test Circuit 2):

   The operating current consumption I_{Power_down} is the current measured going into the BAT pin under the following conditions: V1 = 1.5V and V2 = 1.5V.

8. Resistance between V– and BAT pin (Test Circuit 3):

   Measure the resistance (R_{V_D}) between V– and BAT pins by setting the following conditions: V1 = 1.8V and V2 = 0V.

9. Current sink between V– and VSS (Test Circuit 3):

   Measure the current sink I_V–S between V– and VSS pins by setting the following condition: V1 = 4V.

10. COUT current source when activated High (Test Circuit 4):

    Measure I_COUT current source on the COUT pin by setting the following conditions: V1 = 3.9V, V2 = 0V, and V3 = 3.4V.

11. COUT current sink when activated Low (Test Circuit 4):

    Measure I_COUT current sink on COUT pin by setting the following conditions: V1 = 4.5V, V2 = 0V, and V3 = 0.5V.

12. DOUT current source when activated High (Test Circuit 4):

    Measure I_DOUT current source on DOUT pin by setting the following conditions: V1 = 3.9V, V2 = 0V, and V3 = 3.4V.

13. DOUT current sink when activated Low (Test Circuit 4):

    Measure I_DOUT current sink on DOUT pin by setting the following conditions: V1 = 2.0V, V2 = 0V, and V3 = 0.4V.

14. Overcharge detection delay (Test Circuit 5):

    The overcharge detection delay time t_OVPD is the time delay before the COUT drive output transitions from high to low once the voltage on V1 exceeds the V_OVP threshold. Set V2 = 0V and then increase V1 until BAT input exceeds the V_OVP threshold, then check the time for when COUT goes from high to low.

15. Over-discharge detection delay (Test Circuit 5):

    The over-discharge detection delay time t_UVPD is the time delay before the DOUT drive output transitions from high to low once the voltage on V1 decreases to V_UVP threshold. Set V2 = 0V and then decrease V1 until BAT input reduces to the V_UVPthreshold, then check the time of when DOUT goes from high to low.

16. Discharge overcurrent detection delay (Test Circuit 5):

    The discharge overcurrent detection delay time t_OCDD is the time for DOUT drive output to transition from high to low after the voltage on V2 is increased from 0V to 0.35V. V1 = 3.5V and V2 starts from 0V and increases to trigger threshold.

17. Load short circuit detection delay (Test Circuit 5):

    The load short-circuit detection delay time t_SCCD is the time for DOUT drive output to transition from high to low after the voltage on V2 is increased from 0V to V1 – 1V. V1 = 3.5V and V2 starts from 0V and increases to trigger threshold.

18. Charge overcurrent detection delay (Test Circuit 5):

    The charge overcurrent detection delay time t_OCCD is the time for COUT drive output to transition from high to low after the voltage on V2 is decreased from 0V to –0.3V. V1 = 3.5V and V2 starts from 0V and decreases to trigger threshold.

19. 0V battery charge starting charger voltage (Test Circuit 2):

    The 0V charge for start charging voltage V_0CHA is defined as the voltage between BAT and V– pins at which COUT goes high when voltage on V2 is gradually decreased from a condition of V1 = V2 = 0V.

20. 0V battery charge inhibition battery voltage (Test Circuit 2):

    The 0V charge inhibit for charger voltage V_0INH is defined as the voltage between BAT and VSS pins at which COUT should go low as V1 is gradually decreased from V1 = 2V and V2 = –4V.