If the battery voltage drops below the over-discharge detection voltage (V_UVP) for a time greater than (t_UVPD) the discharge control output, DOUT is switched to a low state and the discharge FET is turned OFF to prevent further discharging of the battery. This is referred to as an over-discharge detection status. In this condition, the V– pin is internally pulled up to BAT by the resistor R_V–D. When this occurs, the voltage difference between V– and BAT pins is 1.3V or lower, and the current consumption of the device is reduced to power-down level I_STANDBY. The current sink I_V–S is not active in power-down state or over-discharge state. The power-down state is released when a charger is connected and the voltage delta between V– and BAT pins is greater than 1.3V.

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is lower than –0.7V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the discharge FET once the battery voltage exceeds over-discharge detection voltage (V_UVP).

If a charger is connected to a battery in over-discharge state and the voltage detected at the V– is higher than –0.7V, the device releases the over-discharge state and allows the DOUT pin to go high and turn ON the discharge FET once the battery voltage exceeds over-discharge detection release hysteresis voltage (V_{UVP +Hys}).