米6体育平台手机版

ZHCSHD3K October 2017 – July 2024 BQ2980 , BQ2982

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RUG|8
- MPQF215A

散热焊盘机械数据 (封装 | 引脚)

RUG|8
- QFND220

订购信息

6.5 Electrical Characteristics

Typical values stated at T_A = 25°C and VDD = 3.6 V. MIN/MAX values stated with T_A = –40°C to +85°C and VDD = 3 to 5 V unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENT CONSUMPTION
I_NORMAL	Normal mode supply current	V_CHG and V_DSG > 5 V, C_LOAD = 8 nF (typical 20 nA⁽¹⁾), VDD > 4.0 V		5	8	µA
I_NORMAL	Normal mode supply current	V_CHG and V_DSG > 5 V, C_LOAD = 8 nF (typical 20 nA⁽¹⁾), UVP < VDD < 3.9 V		4	6	µA
I_FETOFF	Supply current with both FET drivers off	V_CHG = V_DSG ≤ 0.2 V		2	4	µA
I_SHUT	Shutdown current	V_PACK < VBAT, VDD = 1.5 V			0.1	µA
N-CH FET DRIVER, CHG and DSG
A_FETON	FET driver gain factor, the Vgs voltage to FET	V_CHG or V_DSG = VDD + VDD × A_FETON UVP < VDD < 3.9 V C_LOAD = 8 nF	1.65	1.75	1.81	V/V
A_FETON	FET driver gain factor, the Vgs voltage to FET	V_CHG or V_DSG = VDD + VDD × A_FETON VDD > 4.0 V C_LOAD = 8 nF	1.45	1.55	1.68	V/V
V_FETOFF	FET driver off output voltage	V_FETOFF = V_CHG – VSS or V_DSG – VSS C_LOAD = 8 nF			0.2	V
V_{DRIVER_SHUT}	FET driver charge pump shut down voltage	Charge pump enabled when VDD rises to V_{DRIVER_SHUT}	1.95	2	2.1	V
V_{DRIVER_SHUT_HYS}	FET driver charge pump shut down voltage hysteresis	Charge pump disabled when VDD falls to V_{DRIVER_SHUT} – V_{DRIVER_SHUT_HYS}		50		mV
t_rise⁽²⁾	FET driver rise time	C_LOAD = 8 nF, V_CHG or V_DSG rises from VDD to (2 × VDD)		400	800	µs
t_fall	FET driver fall time	C_LOAD = 8 nF, V_CHG or V_DSG fall to V_FETOFF		50	200	µs
I_LOAD	FET driver maximum loading				10	µA
VOLTAGE PROTECTION
V_OVP	Overvoltage detection range	Factory configured, 50-mV step	3750		5200	mV
V_{OVP_ACC}	Overvoltage detection accuracy	T_A = 25°C, CHG/DSG C_LOAD < 1 µA	–10		10	mV
		T_A = 0°C to 60°C, CHG/DSG C_LOAD < 1 µA	–15		15
		T_A = –40°C to +85°C, CHG/DSG C_LOAD < 1 µA	–25		25
V_{OVP_HYS}	Overvoltage release hysteresis voltage	Fixed at 200 mV	150	200	250	mV
V_UVP	Undervoltage detection range	Factory configured, 50-mV step	2200		3000	mV
V_{UVP_ACC}	Undervoltage detection accuracy	T_A = 25°C	–20		20	mV
		T_A = 0°C to 60°C	–30		30	mV
		T_A = –40°C to +85°C	–50		50	mV
V_{UVP_HYS}	Undervoltage release hysteresis voltage	Fixed at 200 mV	150	200	250	mV
R_PACK-VSS	Resistance between PACK and VSS during UV fault		100	300	550	kΩ
CURRENT PROTECTION
V_OC	Overcurrent in charge (OCC) and discharge (OCD) range	Factory configured, 2-mV step. For OCC, the range is negative (min = –64, max = –4).	4		64	mV
V_SCD	Short circuit in discharge threshold	Factory configured		10		mV
				20
				30
				40
				60
				120
				200
V_{OC_ACC}	Overcurrent (OCC, OCD1, OCD2, SCD) detection accuracy	< 20 mV	–1		1	mV
		20 to approximately 55 mV	–3	2	3
		56 to approximately 100 mV	–5		5
		> 100 mV	–12		12
I_PACK-VDD	Current sink between PACK and VDD during current fault. Used for load removal detection		8		24	µA
I_{OCD_REC}	OCD, SCD recovery detection current	Sum of current from VDD and BAT during OCD or SCD fault			55	µA
V_{OC_REL}	OCC fault release threshold	(V_BAT – V_PACK)		100		mV
	OCD, SCD fault release threshold	(V_PACK – V_BAT)		–400		mV
OVERTEMPERATURE PROTECTION⁽²⁾
T_OT	Internal overtemperature threshold	Factory configured		75		°C
T_OT	Internal overtemperature threshold	Factory configured		85		°C
T_{OT_ACC}	Internal overtemperature detection accuracy		–10		10	°C
T_{OT_HYS}	Internal overtemperature hysteresis		8	15	22	°C
PROTECTION DELAY⁽²⁾
t_OVP	Overvoltage detection delay	Factory configured	0.2	0.25	0.3	s
			0.8	1	1.2
			1	1.25	1.5
			3.6	4.5	5.4
t_UVP	Undervoltage detection delay	Factory configured	16	20	24	ms
			76.8	96	115.2
			100	125	150
			115.2	144	172.8
t_OC	Overcurrent (OCC, OCD) detection delay	Factory configured	5.6	8	10.5	ms
			12.4	16	19.6
			16	20	24
			38.4	48	57.6
t_SCD	Short circuit discharge detection delay	Fixed configuration	125	250	375	µs
t_OT	Overtemperature detection delay	Fixed configuration	3.6	4.5	5.4	s
FET OVERRIDE/DEVICE SHUTDOWN CONTROL, CTR
V_IH	High-level input		1			V
V_IL	Low-level input				0.4	V
V_HYS	Hysteresis for V_IH and V_IL		200			mV
R_{PULL_UP}	Effective Internal pull-up resistance (to use with external PTC)	Factory configured if enabled		1.5		MΩ
				5
				8
ZVCHG (0-V Charging)
V_0CHGR	Charger voltage requires to start 0-V charging	BQ2980xy only (ZVCHG is disabled in BQ2982xy). The CHG driver becomes high impedance when VDD < V_0INH.	2			V
V_0INH	Battery voltage that inhibits 0-V charging				1	V

(1) I_NORMAL is impacted by the efficiency of the charge pump driving the CHG and DSG FETs. An ultra-low-gate-leakage FET may be required. I_NORMAL can be significantly higher with FETs with typical I_GSS values of 10 µA. See Selection of Power FET for more details.

(2) Specified by design.