ZHCSHD3K October 2017 – July 2024 BQ2980 , BQ2982
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Overvoltage (OV) Status
- 7.3.2 Undervoltage (UV) Status
- 7.3.3 Overcurrent in Charge (OCC) Status
- 7.3.4 Overcurrent in Discharge (OCD) and Short Circuit in Discharge (SCD) Status
- 7.3.5 Overtemperature (OT) Status
- 7.3.6 Charge and Discharge Driver
- 7.3.7 CTR for FET Override and Device Shutdown
- 7.3.8 CTR for PTC Connection
- 7.3.9 ZVCHG (0-V Charging)
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
8.1.3 Using CTR as FET Driver On/Off Control
Normally, CTR is not designed as a purely on/off control of the FET drivers, because there is a timing constriction on the pin. The following is a list of workarounds to implement the CTR as an on/off switch to the FET drivers.
- Switching CTR from high to low with less than 3.6 s:
If the application only requires turning off the FET drivers in < 3.6 s, then the CTR pin can simply be viewed as an on/off switch of the FET drivers. That means, after the CTR pin is pulled high, the application will pull the CTR pin back low in < 3.6 s.
- Applying a voltage on PACK to prevent the device from entering SHUTDOWN mode:
When the CTR pin is be pulled high for > 3.6 s, there is a chance the device may go into SHUTDOWN mode. If the CTR pin is high for > 5.4 s, the device will be in SHUTDOWN mode. For applications that may use the CTR to keep the FET drivers off for > 3.6 s, the workaround is to keep VPACK within the VDD recommended operating range while the CTR is pulled high to prevent the device from entering SHUTDOWN mode. The device is forced to stay in NORMAL mode with this method.
Because the PACK pin is also connected to the PACK terminal, the system designer should have a blocking diode to protect the GPIO (that controls the CTR pin) from high voltage.
Figure 8-5 PACK Voltage Timing with
Switching CTR as On/Off Control of FET Drivers