The device has a built-in internal temperature sensor for OT protection. The sensor detects OT when the internal temperature measurement is above the internal overtemperature threshold (T_OT). If this condition exists for longer than the OT delay (t_OT), both CHG and DSG outputs are driven to V_FETOFF to turn off the CHG and DSG FETs.

The OT state is released and the CHG and DSG outputs rise to HIGH, that is V_CHG and V_DSG = VDD × (1 + A_FETON), if the internal temperature measurement falls below (T_OT – T_{OT_HYS}).