ZHCS926C May   2012  – May 2021 BQ34Z100

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Power-On Reset
    6. 6.6  Electrical Characteristics: LDO Regulator
    7. 6.7  Electrical Characteristics: Internal Temperature Sensor Characteristics
    8. 6.8  Electrical Characteristics: Low-Frequency Oscillator
    9. 6.9  Electrical Characteristics: High-Frequency Oscillator
    10. 6.10 Electrical Characteristics: Integrating ADC (Coulomb Counter) Characteristics
    11. 6.11 Electrical Characteristics: ADC (Temperature and Cell Measurement) Characteristics
    12. 6.12 Electrical Characteristics: Data Flash Memory Characteristics
    13. 6.13 Timing Requirements: HDQ Communication
    14. 6.14 Timing Requirements: I2C-Compatible Interface
    15. 6.15 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1  Data Commands
        1. 7.2.1.1 Standard Data Commands
        2. 7.2.1.2 Control(): 0x00/0x01
          1. 7.2.1.2.1  CONTROL_STATUS: 0x0000
          2. 7.2.1.2.2  DEVICE TYPE: 0x0001
          3. 7.2.1.2.3  FW_VERSION: 0x0002
          4. 7.2.1.2.4  HW_VERSION: 0x0003
          5. 7.2.1.2.5  RESET_DATA: 0x0005
          6. 7.2.1.2.6  PREV_MACWRITE: 0x0007
          7. 7.2.1.2.7  CHEM ID: 0x0008
          8. 7.2.1.2.8  BOARD_OFFSET: 0x0009
          9. 7.2.1.2.9  CC_OFFSET: 0x000A
          10. 7.2.1.2.10 CC_OFFSET_SAVE: 0x000B
          11. 7.2.1.2.11 DF_VERSION: 0x000C
          12. 7.2.1.2.12 SET_FULLSLEEP: 0x0010
          13. 7.2.1.2.13 STATIC_CHEM_DF_CHKSUM: 0x0017
          14. 7.2.1.2.14 SEALED: 0x0020
          15. 7.2.1.2.15 IT ENABLE: 0x0021
          16. 7.2.1.2.16 RESET: 0x0041
          17. 7.2.1.2.17 EXIT_CAL: 0x0080
          18. 7.2.1.2.18 ENTER_CAL: 0x0081
          19. 7.2.1.2.19 OFFSET_CAL: 0x0082
        3. 7.2.1.3 StateOfCharge(): 0x02/0x03
        4. 7.2.1.4 RemainingCapacity(): 0x04/0x05
        5. 7.2.1.5 FullChargeCapacity(): 0x06/07
        6. 7.2.1.6 Voltage(): 0x08/0x09
        7. 7.2.1.7 AverageCurrent(): 0x0A/0x0B
        8. 7.2.1.8 Temperature(): 0x0C/0x0D
        9. 7.2.1.9 Flags(): 0x0E/0x0F
      2. 7.2.2  Extended Data Commands
        1. 7.2.2.1  AtRate(): 0X10/0x11
        2. 7.2.2.2  AtRateTimeToEmpty(): 0x12/0x13
        3. 7.2.2.3  Current(): 0x10/0x11
        4. 7.2.2.4  NominalAvailableCapacity(): 0x14/0x15
        5. 7.2.2.5  FullAvailableCapacity(): 0x16/0x17
        6. 7.2.2.6  TimeToEmpty(): 0x18/0x19
        7. 7.2.2.7  TimeToFull(): 0x1A/0x1B
        8. 7.2.2.8  StandbyCurrent(): 0x1C/0x1D
        9. 7.2.2.9  StandbyTimeToEmpty(): 0x1E/0x1F
        10. 7.2.2.10 MaxLoadCurrent(): 0x20/0x21
        11. 7.2.2.11 MaxLoadTimeToEmpty(): 0x22/0x23
        12. 7.2.2.12 AvailableEnergy(): 0x24/0x25
        13. 7.2.2.13 AveragePower(): 0x26/0x27
        14. 7.2.2.14 TimeToEmptyAtConstantPower(): 0x28/0x29
        15. 7.2.2.15 InternalTemp(): 0x2A/0x2B
        16. 7.2.2.16 CycleCount(): 0x2C/0x2D
        17. 7.2.2.17 StateOfHealth(): 0x2E/0x2F
        18. 7.2.2.18 ChargeVoltage(): 0x30/0x31
        19. 7.2.2.19 ChargeCurrent(): 0x32/0x33
        20. 7.2.2.20 PassedCharge(): 0x34/0x35
        21. 7.2.2.21 DOD0(): 0x36/0x37
        22. 7.2.2.22 SelfDischargeCurrent(): 0x38/0x39
        23. 7.2.2.23 PackConfiguration(): 0x3A/0x3B
        24. 7.2.2.24 DesignCapacity(): 0x3C/0x3D
        25. 7.2.2.25 DataFlashClass(): 0x3E
        26. 7.2.2.26 DataFlashBlock(): 0x3F
        27. 7.2.2.27 AuthenticateData/BlockData(): 0x40…0x53
        28. 7.2.2.28 AuthenticateChecksum/BlockData(): 0x54
        29. 7.2.2.29 BlockData(): 0x55…0x5F
        30. 7.2.2.30 BlockDataChecksum(): 0x60
        31. 7.2.2.31 BlockDataControl(): 0x61
        32. 7.2.2.32 DeviceNameLength(): 0x62
        33. 7.2.2.33 DeviceName(): 0x63…0x6A
      3. 7.2.3  Data Flash Interface
        1. 7.2.3.1 Accessing Data Flash
        2. 7.2.3.2 Manufacturer Information Block
        3. 7.2.3.3 Access Modes
        4. 7.2.3.4 Sealing/Unsealing Data Flash Access
      4. 7.2.4  Data Flash Summary
      5. 7.2.5  Fuel Gauging
      6. 7.2.6  Impedance Track Variables
        1. 7.2.6.1  Load Mode
        2. 7.2.6.2  Load Select
        3. 7.2.6.3  Reserve Cap-mAh
        4. 7.2.6.4  Reserve Cap-mWh/cWh
        5. 7.2.6.5  Design Energy Scale
        6. 7.2.6.6  Dsg Current Threshold
        7. 7.2.6.7  Chg Current Threshold
        8. 7.2.6.8  Quit Current, Dsg Relax Time, Chg Relax Time, and Quit Relax Time
        9. 7.2.6.9  Qmax
        10. 7.2.6.10 Update Status
        11. 7.2.6.11 Avg I Last Run
        12. 7.2.6.12 Avg P Last Run
        13. 7.2.6.13 Delta Voltage
        14. 7.2.6.14 Ra Tables
        15. 7.2.6.15 Pack Configuration Register
          1. 7.2.6.15.1 Pack Configuration B Register
          2. 7.2.6.15.2 Pack Configuration C Register
      7. 7.2.7  Voltage Division and Calibration
        1. 7.2.7.1 1S Example
        2. 7.2.7.2 7S Example
        3. 7.2.7.3 Autocalibration
      8. 7.2.8  Temperature Measurement
      9. 7.2.9  Overtemperature Indication
        1. 7.2.9.1 Overtemperature: Charge
        2. 7.2.9.2 Overtemperature: Discharge
      10. 7.2.10 Charging and Charge Termination Indication
      11. 7.2.11 X10 Mode
      12. 7.2.12 Remaining State of Charge LED Indication
      13. 7.2.13 Alert Signal
      14. 7.2.14 Communications
        1. 7.2.14.1 Authentication
        2. 7.2.14.2 Key Programming
        3. 7.2.14.3 Executing an Authentication Query
        4. 7.2.14.4 HDQ Single-Pin Serial Interface
        5. 7.2.14.5 I2C Interface
      15. 7.2.15 Power Control
        1. 7.2.15.1 Reset Functions
        2. 7.2.15.2 Wake-Up Comparator
        3. 7.2.15.3 Flash Updates
    3. 7.3 Device Functional Modes
      1. 7.3.1 NORMAL Mode
      2. 7.3.2 SLEEP Mode
      3. 7.3.3 FULL SLEEP Mode
  8. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Step-by-Step Design Procedure
          1. 8.1.2.1.1 STEP 1: Review and Modify the Data Flash Configuration Data.
          2. 8.1.2.1.2 STEP 2: Review and Modify the Data Flash Configuration Registers.
          3. 8.1.2.1.3 STEP 3: Design and Configure the Voltage Divider.
          4. 8.1.2.1.4 STEP 4: Determine the Sense Resistor Value.
          5. 8.1.2.1.5 STEP 5: Review and Modify the Data Flash Gas Gauging Configuration, Data, and State.
          6. 8.1.2.1.6 STEP 6: Determine and Program the Chemical ID.
          7. 8.1.2.1.7 STEP 7: Calibrate.
          8. 8.1.2.1.8 STEP 8: Run an Optimization Cycle.
      3. 8.1.3 Battery Chemistry Configuration
        1. 8.1.3.1 Battery Chemistry Charge Termination
      4. 8.1.4 Replaceable Battery Systems
      5. 8.1.5 Digital Interface Options
      6. 8.1.6 Display Options
      7. 8.1.7 Application Curves
      8. 8.1.8 Special Applications
        1. 8.1.8.1 Operation Configuration B Register
        2. 8.1.8.2 Operation Configuration C Register
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Introduction
      2. 10.1.2 Power Supply Decoupling Capacitor
      3. 10.1.3 Capacitors
      4. 10.1.4 Communication Line Protection Components
    2. 10.2 Layout Example
      1. 10.2.1 Ground System
      2. 10.2.2 Kelvin Connections
      3. 10.2.3 Board Offset Considerations
      4. 10.2.4 ESD Spark Gap
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10.2.3 Board Offset Considerations

Although the most important component for board offset reduction is the decoupling capacitor for VCC, additional benefit is possible by using this recommended pattern for the coulomb counter differential low-pass filter network. Maintain the symmetrical placement pattern shown for optimum current offset performance. Use symmetrical shielded differential traces, if possible, from the sense resistor to the 100-Ω resistors, as shown in Figure 10-2.

GUID-C2F6F1FF-8AF8-4DED-93D5-15C2EBA38CE2-low.png Figure 10-2 Differential Connection Between SRP and SRN Pins with Sense Resistor
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