11.1 Layout Guidelines

• Keep the trace resistance as low as possible on AC1, AC2, and BAT.
• Detection and resonant capacitors must be as close to the device as possible.
• COMM, CLAMP, and BOOT capacitors must be placed as close to the device as possible.
• Via interconnect on PGND net is critical for appropriate signal integrity and proper thermal performance.
• High-frequency bypass capacitors must be placed close to RECT and OUT pins.
• ILIM and FOD resistors are important signal paths and the loops in those paths to PGND must be minimized.

Signal and sensing traces are the most sensitive to noise; the sensing signal amplitudes are usually measured in mV, which is comparable to the noise amplitude. Make sure that these traces are not being interfered by the noisy and power traces. AC1, AC2, BOOT1, BOOT2, COMM1, and COMM2 are the main source of noise in the board. These traces must be shielded from other components in the board. It is usually preferred to have a ground copper area placed underneath these traces to provide additional shielding. Also, make sure they do not interfere with the signal and sensing traces. The PCB must have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, one via per capacitor for small-signal components).

For a 1-A fast charge current application, the current rating for each net is as follows:

• AC1 = AC2 = 1.2 A
• OUT = 1 A
• RECT = 100 mA (RMS)
• COMMx = 300 mA
• CLAMPx = 500 mA
• All others can be rated for 10 mA or less

11.2 Layout Example

Figure 38. Layout Schematic