8.3.1 Dynamic Rectifier Control

The Dynamic Rectifier Control algorithm offers the end-system designer optimal transient response for a given maximum output current setting. This is achieved by providing enough voltage headroom across the internal regulator (LDO) at light loads in order to maintain regulation during a load transient. The WPC system has a relatively slow global feedback loop where it can take up to 150 ms to converge on a new rectifier voltage target. Therefore, a transient response is dependent on the loosely coupled transformer's output impedance profile. The Dynamic Rectifier Control allows for a 1.5-V change in rectified voltage before the transient response is observed at the output of the internal regulator (output of the bq5102x device). A 1-A application allows up to a 2-Ω output impedance. The Dynamic Rectifier Control behavior is illustrated in Figure 12.

8.3.2 Dynamic Power Scaling

The Dynamic Power Scaling feature allows for the loss characteristics of the bq5102x device to be scaled based on the maximum expected output power in the end application. This effectively optimizes the efficiency for each application. This feature is achieved by scaling the loss of the internal LDO based on a percentage of the maximum output current. Note that the maximum output current is set by the K_ILIM term and the R_ILIM resistance (where R_ILIM = K_ILIM / I_ILIM). The flow diagram in Figure 12 shows how the rectifier is dynamically controlled (Dynamic Rectifier Control) based on a fixed percentage of the I_ILIM setting. Table 1 summarizes how the rectifier behavior is dynamically adjusted based on two different R_ILIM settings. Table 1 shows I_MAX, which is typically lower than I_ILIM (about 20% lower). See section RILIM Calculations about setting the ILIM resistor for more details.

Table 1 shows the shift in the Dynamic Rectifier Control behavior based on the two different R_ILIM settings. With the rectifier voltage (V_RECT) as the input to the internal LDO, this adjustment in the Dynamic Rectifier Control thresholds dynamically adjusts the power dissipation across the LDO where,

Equation 1.

Figure 21 shows how the system efficiency is improved due to the Dynamic Power Scaling feature. Note that this feature balances efficiency with optimal system transient response.

8.3.3 VO_REG Calculations

The bq5102x device allows the designer to set the output voltage by setting a feedback resistor divider network from the OUT pin to the VO_REG pin, as seen in Figure 8. The resistor divider network should be chosen so that the voltage at the VO_REG pin is 0.5 V at the desired output voltage. For the device bq51021 which has I²C enabled, this applies to the default I²C code for VO_REG shown in I²C register in Figure 8.

Figure 8. VO_REG Network

Choose the desired output voltage V_OUT and R₆:

Equation 2.

Equation 3.

8.3.4 RILIM Calculations

The bq5102x device includes a means of providing hardware overcurrent protection (I_ILIM) through an analog current regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable output current (for example, current compliance). The R_ILIM resistor size also sets the thresholds for the dynamic rectifier levels providing efficiency tuning per each application’s maximum system current. The calculation for the total R_ILIM resistance is as follows:

R_ILIM allows for the ILIM pin to reach 1.2 V at an output current equal to I_ILIM. When choosing R_ILIM, two options are possible.

If the user's application requires an output current equal to or greater than the external I_ILIM that the circuit is designed for (input current limit on the charger where the receiver device is tied higher than the external I_ILIM), ensure that the downstream charger is capable of regulating the voltage of the input into which the receiver device output is tied to by lowering the amount of current being drawn. This ensures that the receiver output does not drop to 0. Such behavior is referred to as VIN DPM in TI chargers. Unless such behavior is enabled on the charger, the charger will pull the output of the receiver device to ground when the receiver device enters current regulation. If the user's applications are designed to extract less than the I_ILIM (1-A maximum), typical designs should leave a design margin of at least 10%, so that the voltage at ILIM pin reaches 1.2 V when 10% more than maximum current is drawn from the output. Such a design would have input current limit on the charger lower than the external ILIM of the receiver device. In both cases, the charger must be capable of regulating the current drawn from the device to allow the output voltage to stay at a reasonable value. This same behavior is also necessary during the WPC communication. The following calculations show how such a design is achieved:

When referring to the application diagram shown in Typical Applications, R_ILIM is the sum of the R₁ and R_FOD resistance (that is, the total resistance from the ILIM pin to GND). R_FOD is chosen according to the application. The tool for calculating R_FOD can be obtained by contacting your TI representative. Use R_FOD to allow the receiver implementation to comply with WPC v1.1 requirements related to received power accuracy. For the device bq51021 which has I²C enabled, this applies to the default I²C code for IO_REG (100%) shown in I²C register in Figure 8.

8.3.5 Adapter Enable Functionality

The bq5102x device can also help manage the multiplexing of adapter power to the output and can turn off the TX when the adapter is plugged in and is above the V_AD-EN. After the adapter is plugged in and the output turns off, the RX device sends an EOC to the TX. In this case, the AD_EN pins are then pulled to approximately 4 V below AD, which allows the device turn on the back-to-back PMOS connected between AD and OUT (Figure 28).

Both the AD and AD-EN pins are rated at 30 V, while the OUT pin is rated at 20 V. It must also be noted that it is required to connect a back-to-back PMOS between AD and OUT so that voltage is blocked in both directions. Also, when AD mode is enabled, no load can be pulled from the RECT pin as this could cause an internal device overvoltage in the bq5102x device.

For the device bq51021, the wired power will always take priority over wireless power, and thus when the adapter is plugged in, the device will first send an EPT to the TX and then will send allow for up to 30 ms after disabling the output allowing the WPG to go high impedance. It will then allow the wired power to be delivered to the output by pulling the AD_EN below the AD pin to allow the adapter power to be passed on the output.

For the device bq51020, the EN1 and EN2 pins will determine the preference of wired or wireless power. Table 2 shows the EN1 and EN2 state and the corresponding device selection.

8.3.6 Turning Off the Transmitter

WPC v1.1 specification allows the receiver to turn off the transmitter and put the system in a low-power standby mode. There are two different ways to accomplish this with the bq5102x device. The first method is by using the TS/CTRL pin. By pulling the pin high or low, EPT can be sent to the transmitter.

Pulling the TS/CTRL pin high will send EPT (code 0x01), which corresponds to charge complete. The transmitter will then respond to this EPT code as per the transmitter's design. After this EPT code is sent, some transmitters will then periodically check to make sure that the receiver is not looking for a refresh charge on the battery. The period of how often the transmitter checks varies based on the transmitter design. The transmitter will use the digital ping or a shortened version of it to check the receiver status. It is this energy on the digital ping that the receiver uses to indicate whether it is still sitting on the transmitter surface by storing the energy from the digital ping on the capacitor attached to the TMEM pin. The cap voltage (determined by the periodicity of the digital ping and the bleed off resistor attached in parallel to the TMEM cap) determine when the receiver indicates that it is no longer on the surface of the transmitter by allowing the PD_DET pin to go high impedance.

The TS/CTRL pin can also be pulled low. This will allow the receiver to determine that the host processor would like to shut down the transmitter because of thermal reasons. Therefore, the receiver will send EPT (code 0x03) indicating an overtemperature event.

8.3.7 Communication Current Limit

Communication current limit is a feature that allows for error free communication to happen between the RX and TX in the WPC mode. This is done by decoupling the coil from the load transients by limiting the output current during communication with the TX. The communication current limit is set according to the Table 4. The communication current limit can be disabled by pulling CM_ILIM pin high (> 1.4 V) or enabled by pulling the CM_ILIM pin low. There is an internal pulldown that enables communication current limit when the CM_ILIM pin is left floating.

When the communication current limit is enabled, the amount of current that the load can draw is limited. If the charger in the system does not have a VIN-DPM feature, the output of the receiver will collapse if communication current limit is enabled. To disable communication current limit, pull CM_ILIM pin high.

8.3.8 PD_DETand TMEM

PD_DET is an open-drain pin that goes low based on the voltage of the TMEM pin. When the voltage of TMEM is higher than 1.6 V, PD_DET will be low. The voltage on the TMEM pin depends on capturing the energy from the digital ping from the transmitter and storing it on the C₅ capacitor in Figure 9. After the receiver sends an EPT (charge complete), the transmitter shuts down and goes into a low-power mode. After this EPT code is sent, some transmitters will then periodically check to make sure that the receiver is not looking for a refresh charge on the battery. The period of how often the transmitter checks varies based on the transmitter design. The transmitter will use the digital ping or a shortened version of it to check the receiver status. It is this energy on the digital ping that the receiver uses to indicate whether it is still sitting on the transmitter surface by storing the energy from the digital ping on the capacitor attached to the TMEM pin. The cap voltage (determined by the periodicity of the digital ping and the bleed off resistor attached in parallel to the TMEM cap) determine when the receiver indicates that it is no longer on the surface of the transmitter by allowing the PD_DET pin to go high impedance. The energy from the digital ping can be stored on the TMEM pin until the next digital ping refreshes the capacitor. A bleedoff resistor R_MEMcan be chosen in parallel with C₅ that sets the time constant so that the TMEM pin will fall below 1.6 V once the next ping timer expires. The duration between digital pings is indeterminate and depends on each transmitter manufacturer.

Figure 9. TMEM Configuration

Set capacitor on C₅ = TMEM to 2.2 µF. Resistor R_MEM across C₅ can be set by understanding the duration between digital pings (tping). Set the resistor such that:

Equation 8.

PD_DET typically requires a pullup resistor to an external source. The choice of the pullup resistor determines load regulation; the suggested values for the pullup resistor are between 5.6 and 100 kΩ. The higher values offer better load regulation.

8.3.9 TS/CTRL

The bq5102x device includes a ratio metric external temperature sense function. The temperature sense function has a low ratio metric threshold which represents a hot condition. TI recommends an external temperature sensor in order to provide safe operating conditions for the receiver product. This pin is best used for monitoring the surface that can be exposed to the end user (for example, place the negative temperature coefficient (NTC) resistor closest to the user touch point on the back cover). A resistor in series or parallel can be inserted to adjust the NTC to match the trip point of the device. The implementation in Figure 10 shows the series-parallel resistor implementation for setting the threshold at which V_TS-HOT is reached. Once the V_TS-HOT threshold is reached, the device will send an EPT – overtemperature signal for a WPC transmitter.

Figure 10. NTC Resistor Setup

Figure 10 shows a parallel resistor setup that can be used to adjust the trip point of V_TS-HOT. T_S-HOT is VS. After the NTC is chosen and R_NTCHOT at V_TS-HOT is determined from the data sheet of the NTC, Equation 9 can be used to calculate R₁ and R₃. In many cases depending on the NTC resistor, R₁ or R₃ can be omitted. To omit R₁, set R₁ to 0, and to omit R₃, set R₃ to 10 MΩ.

Equation 9.

8.3.10 I²C Communication

Only bq51021

The bq5102x device allows for I²C communication with the internal CPU. In case the I²C is not used, ground SCL and SDA. See Register Maps for more information.

8.3.11 Input Overvoltage

If the input voltage suddenly increases in potential for some condition (for example, a change in position of the equipment on the charging pad), the voltage-control loop inside the bq5102x device becomes active, and prevents the output from going beyond V_OUT(REG). The receiver then starts sending back error packets every 30 ms until the input voltage comes back to an acceptable level, and then maintains the error communication every 250 ms.

If the input voltage increases in potential beyond V_RECT-OVP, the device switches off the LDO and informs the primary to bring the voltage back to V_RECT(REG). In addition, a proprietary voltage protection circuit is activated by means of C_CLAMP1 and C_CLAMP2 that protects the device from voltages beyond the maximum rating of the device.

Table 5. Wireless Power Supply Current Register 1 (READ / WRITE)

Table 6. Wireless Power Supply Current Register 2 (READ / WRITE)

Table 7. I²C Mailbox Register (READ / WRITE)

Table 8. Wireless Power Supply FOD RAM (READ / WRITE)

Table 9. Wireless Power User Header RAM (WRITE)

Table 10. Wireless Power USER V_RECT Status RAM (READ)⁽¹⁾

Table 11. Wireless Power V_OUT Status RAM (READ)⁽¹⁾

Table 12. Wireless Power REC PWR Most Significant Byte Status RAM (READ)

Table 13. Wireless Power Prop Packet Payload RAM Byte 0 (WRITE)

Table 14. Wireless Power Prop Packet Payload RAM Byte 1 (WRITE)

Table 15. Wireless Power Prop Packet Payload RAM Byte 2 (WRITE)

Table 16. Wireless Power Prop Packet Payload RAM Byte 3 (WRITE)