VUVLO |
Undervoltage lockout |
VRECT: 0 to 3 V |
|
2.8 |
2.9 |
V |
VHYS-UVLO |
Hysteresis on UVLO |
VRECT: 3 to 2 V |
|
393 |
|
mV |
VRECT-OVP |
Input overvoltage threshold |
VRECT: 5 to 16 V |
14.6 |
15.1 |
15.6 |
V |
VHYS-OVP |
Hysteresis on OVP |
VRECT: 16 to 5 V |
|
1.5 |
|
V |
VRECT(REG) |
Voltage at RECT pin set by communication with primary |
|
VOUT + 0.120 |
|
Lower of VOUT + 0.2 or 11.0 |
V |
VRECT(TRACK) |
VRECT regulation above VOUT |
VILIM = 1.2 V |
|
140 |
|
mV |
ILOAD-HYS |
ILOAD hysteresis for dynamic VRECT thresholds as a % of IILIM |
ILOAD falling |
|
4% |
|
|
VRECT-DPM |
Rectifier undervoltage protection, restricts IOUT at VRECT-DPM |
|
3 |
3.1 |
3.2 |
V |
VRECT-REV |
Rectifier reverse voltage protection with a supply at the output |
VRECT-REV = VOUT – VRECT, VOUT = 10 V |
|
8.8 |
9.2 |
V |
QUIESCENT CURRENT |
IOUT(standby) |
Quiescent current at the output when wireless power is disabled |
VOUT ≤ 5 V, 0°C ≤ TJ ≤ 85°C |
|
20 |
35 |
µA |
ILIM SHORT CIRCUIT |
RILIM-SHORT |
Highest value of RILIM resistor considered a fault (short). Monitored for IOUT > 100 mA |
RILIM: 200 to 50 Ω. IOUT latches off, cycle power to reset |
|
215 |
230 |
Ω |
tDGL-Short |
Deglitch time transition from ILIM short to IOUT disable |
|
|
1 |
|
ms |
ILIM_SC |
ILIM-SHORT,OK enables the ILIM short comparator when IOUT is greater than this value |
ILOAD: 0 to 200 mA |
110 |
125 |
140 |
mA |
ILIM-SHORT,OK HYSTERESIS |
Hysteresis for ILIM-SHORT,OK comparator |
ILOAD: 200 to 0 mA |
|
20 |
|
mA |
IOUT-CL |
Maximum output current limit |
Maximum ILOAD that can be delivered for 1 ms when ILIM is shorted |
|
3.7 |
|
A |
OUTPUT |
VO_REG |
Feedback voltage set point |
ILOAD = 2000 mA, VO_REG resistor divider ratio = 9:1 |
0.4968 |
0.5019 |
0.5077 |
V |
ILOAD = 1 mA, VO_REG resistor divider ratio = 9:1 |
0.4971 |
0.5017 |
0.5079 |
ILOAD = 1000 mA, VO_REG resistor divider ratio = 19:1 |
0.4977 |
0.5027 |
0.5091 |
ILOAD = 1 mA, VO_REG resistor divider ratio = 19:1 |
0.4978 |
0.5029 |
0.5098 |
KILIM |
Current programming factor for hardware short circuit protection |
RILIM = KILIM / IILIM, where IILIM is the hardware current limit IOUT = 900 mA |
|
842 |
|
AΩ |
IOUT_RANGE |
Current limit programming range |
|
|
|
2300 |
mA |
ICOMM |
Output current limit during communication |
IOUT ≥ 400 mA |
|
IOUT – 50 |
|
mA |
100 mA ≤ IOUT < 400 mA |
|
IOUT + 50 |
|
IOUT < 100 mA |
|
200 |
|
tHOLD-OFF |
Hold off time for the communication current limit during startup |
|
|
1 |
|
s |
TS/CTRL |
VTS-Bias |
TS bias voltage (internal) |
ITS-Bias < 100 µA and communication is active (periodically driven, see tTS/CTRL-Meas) |
|
1.8 |
|
V |
VCTRL-HI |
CTRL pin threshold for a high |
VTS/CTRL: 50 to 150 mV |
90 |
105 |
120 |
mV |
TTS/CTRL-Meas |
Time period of TS/CTRL measurements, when TS is being driven |
TS bias voltage is only driven when power packets are sent |
|
|
1700 |
ms |
VTS-HOT |
Voltage at TS pin when device shuts down |
|
|
0.38 |
|
V |
THERMAL PROTECTION |
TJ(OFF) |
Thermal shutdown temperature |
|
|
155 |
|
°C |
TJ(OFF-HYS) |
Thermal shutdown hysteresis |
|
|
20 |
|
°C |
OUTPUT LOGIC LEVELS ON WPG |
VOL |
Open-drain WPG pin |
ISINK = 5 mA |
|
|
550 |
mV |
IOFF,STAT |
WPG leakage current when disabled |
VWPG = 20 V |
|
|
1 |
µA |
COMM PIN |
RDS-ON(COMM) |
COMM1 and COMM2 |
VRECT = 2.6 V |
|
1 |
|
Ω |
ƒCOMM |
Signaling frequency on COMMx pin for WPC |
|
|
2.00 |
|
Kbps |
IOFF,COMM |
COMMx pin leakage current |
VCOMM1 = 20 V, VCOMM2 = 20 V |
|
|
1 |
µA |
CLAMP PIN |
RDS-ON(CLAMP) |
CLAMP1 and CLAMP2 |
|
|
0.5 |
|
Ω |
ADAPTER ENABLE |
VAD-EN |
VAD rising threshold voltage |
VAD 0 V to 5 V |
3.5 |
3.6 |
3.8 |
V |
VAD-EN-HYS |
VAD-EN hysteresis |
VAD 5 V to 0 V |
|
450 |
|
mV |
IAD |
Input leakage current |
VRECT = 0 V, VAD = 5 V |
|
|
50 |
μA |
RAD_EN-OUT |
Pullup resistance from AD-EN to OUT when adapter mode is disabled and VOUT > VAD |
VAD = 0 V, VOUT = 5 V |
|
230 |
350 |
Ω |
VAD_EN-ON |
Voltage difference between VAD and VAD-EN when adapter mode is enabled |
VAD = 5 V, 0°C ≤ TJ ≤ 85°C |
4 |
4.5 |
5 |
V |
VAD = 9 V, 0°C ≤ TJ ≤ 85°C |
3 |
6 |
7 |
V |
SYNCHRONOUS RECTIFIER |
ISYNC-EN |
IOUT at which the synchronous rectifier enters half synchronous mode |
IOUT: 200 to 0 mA |
|
100 |
|
mA |
ISYNC-EN-HYST |
Hysteresis for IOUT,RECT-EN (full-synchronous mode enabled) |
IOUT: 0 to 200 mA |
|
40 |
|
mA |
VHS-DIODE |
High-side diode drop when the rectifier is in half synchronous mode |
IAC-VRECT = 250 mA, and TJ = 25°C |
|
0.7 |
|
V |
I2C |
VIL |
Input low threshold level SDA |
V(PULLUP) = 1.8 V, SDA |
|
|
0.4 |
V |
VIH |
Input high threshold level SDA |
V(PULLUP) = 1.8 V, SDA |
1.4 |
|
|
V |
VIL |
Input low threshold level SCL |
V(PULLUP) = 1.8 V, SCL |
|
|
0.4 |
V |
VIH |
Input high threshold level SCL |
V(PULLUP) = 1.8 V, SCL |
1.4 |
|
|
V |
|
I2C speed |
Typical |
|
100 |
|
kHz |