ZHCSC37A February 2014 – July 2014
PRODUCTION DATA.
- 1 特性
- 2 应用范围
- 3 说明
- 4 简化电路原理图
- 5 修订历史记录
- 6 Device Comparison Table
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Dynamic Rectifier Control
- 9.3.2 Dynamic Power Scaling
- 9.3.3 VO_REG and VIREG Calculations
- 9.3.4 RILIM Calculations
- 9.3.5 Adapter Enable Functionality
- 9.3.6 Turning Off the Transmitter
- 9.3.7 CM_ILIM
- 9.3.8 PD_DET and TMEM
- 9.3.9 TS, Both WPC and PMA
- 9.3.10 I2C Communication
- 9.3.11 Input Overvoltage
- 9.4 Device Functional Modes
- 9.5 Register Maps
-
10Application and Implementation
- 10.1 Application Information
- 10.2
Typical Applications
- 10.2.1
Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output With 1-A Maximum Current
- 10.2.1.1 Design Requirements
- 10.2.1.2
Detailed Design Procedure
- 10.2.1.2.1 Output Voltage Set Point
- 10.2.1.2.2 Output and Rectifier Capacitors
- 10.2.1.2.3 Maximum Output Current Set Point
- 10.2.1.2.4 TERM Resistor
- 10.2.1.2.5 Setting LPRB1 and LPRB2 Resistors
- 10.2.1.2.6 I2C
- 10.2.1.2.7 Communication Current Limit
- 10.2.1.2.8 Receiver Coil
- 10.2.1.2.9 Series and Parallel Resonant Capacitors
- 10.2.1.2.10 Communication, Boot and Clamp Capacitors
- 10.2.1.3 Application Curves
- 10.2.2 bq51221 Embedded in System Board
- 10.2.3 bq51221 Implemented in Back Cover
- 10.2.1
Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output With 1-A Maximum Current
- 11Power Supply Recommendations
- 12Layout
- 13器件和文档支持
- 14机械封装和可订购信息
7 Pin Configuration and Functions
YFP
42 Pins
(Top View)
Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NUMBER | ||
| AC1 | B1, B2, B3 | I | AC input power from receiver resonant tank |
| AC2 | B4, B5, B6 | I | |
| AD | E2 | I | Adapter sense pin |
| AD-EN | E3 | O | Push-pull driver for PFET that can pass AD input to the OUT pin; used for adapter mux control |
| BOOT1 | C1 | O | Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier |
| BOOT2 | C6 | O | |
| COMM1 | F1 | O | Open-drain FETs used to communicate with primary by varying reflected impedance |
| COMM2 | F6 | O | |
| CLAMP1 | E1 | O | Open-drain FETs used to clamp the secondary voltage by providing low impedance across secondary |
| CLAMP2 | E6 | O | |
| CM_ILIM | G3 | I | Enables or disables communication current limit; can be pulled high or low to disable or enable communication current limit |
| FOD | F2 | I | Input that is used for scaling the received power message |
| ILIM | G2 | I/O | Output current or overcurrent level programming pin |
| LPRB 1 | F5 | O | Open drain – active to help drive RECT voltage high at light load on a PMA TX |
| LPRB 2 | G6 | ||
| OUT | D1, D2, D3, D4, D5, D6 | O | Output pin, used to deliver power to the load |
| PD_DET | G6 | O | Open drain output that allows user to sense when receiver is on transmitter |
| PGND | A1, A2, A3, A4, A5, A6 | — | Power and logic ground |
| RECT | C2, C3, C4, C5 | O | Filter capacitor for the internal synchronous rectifier |
| SCL | E4 | I | SCL and SDA are used for I2C communication |
| SDA | F4 | I | |
| TERM, LPRBEN | F3 | I | Sets termination current as a percentage of IILIM as TERM pin. When TERM resistor is populated, LPRB pins are enabled with appropriate function |
| TMEM | G5 | O | TMEM allows capacitor to be connected to GND so energy from transmitter ping can be stored to retain memory of state |
| TS/CTRL | G4 | I | Temperature sense. Can be pulled high to send end power transfer (EPT) or end of charge (EOC) to TX |
| VIREG | E5 | I | Rectifier voltage feedback |
| VO_REG | G1 | I | Sets the regulation voltage for output |
| WPG | F5 | O | Open-drain output that allows user to sense when power is transferred to load |