ZHCSFC3A July   2016  – August 2016

PRODUCTION DATA.  

1. 1 特性
2. 2 应用范围
3. 3 说明
4. 4 修订历史记录
5. 5 Device Comparison Table
6. 6 Pin Configuration and Functions
7. 7 Specifications
   1. 7.1 Absolute Maximum Ratings
   2. 7.2 ESD Ratings
   3. 7.3 Recommended Operating Conditions
   4. 7.4 Thermal Information
   5. 7.5 Electrical Characteristics
   6. 7.6 Typical Characteristics
8. 8 Detailed Description
   1. 8.1 Overview
   2. 8.2 Functional Block Diagram
   3. 8.3 Feature Description
      1. 8.3.1  Dynamic Rectifier Control
      2. 8.3.2  Dynamic Power Scaling
      3. 8.3.3  VO_REG and VIREG Calculations
      4. 8.3.4  RILIM Calculations
      5. 8.3.5  Adapter Enable Functionality
      6. 8.3.6  Turning Off the Transmitter
         1. 8.3.6.1 WPC End Power Transfer (EPT)
         2. 8.3.6.2 PMA EOC
      7. 8.3.7  CM_ILIM
      8. 8.3.8  PD_DET and TMEM
      9. 8.3.9  TS, Both WPC and PMA
      10. 8.3.10 I2C Communication
      11. 8.3.11 Input Overvoltage
   4. 8.4 Device Functional Modes
   5. 8.5 Register Maps
      1. 8.5.1  Wireless Power Supply Current Register 1 (address = 0x01) [reset = 00000001]
      2. 8.5.2  Wireless Power Supply Current Register 2 (address = 0x02) [reset = 00000111 ]
      3. 8.5.3  I2C Mailbox Register (address = 0xE0) [reset = 10000000 ]
      4. 8.5.4  Wireless Power Supply FOD RAM Register (address = 0xE1) [reset =00000000 ]
      5. 8.5.5  Wireless Power User Header RAM Register (address = 0xE2) [reset = 00000000]
      6. 8.5.6  Wireless Power USER VRECT Status RAM Register (address = 0xE3) [reset = 00000000]
      7. 8.5.7  Wireless Power VOUT Status RAM Register (address = 0xE4) [reset = 00000000]
      8. 8.5.8  Wireless Power REC PWR Byte Status RAM Register (address = 0xE8) [reset = 00000000]
      9. 8.5.9  Wireless Power Mode Indicator Register (address = 0xEF) [reset = 00000000]
      10. 8.5.10 Wireless Power Prop Packet Payload RAM Byte 0 Register (address = 0xF1) [reset = 00000000]
      11. 8.5.11 Wireless Power Prop Packet Payload RAM Byte 1 Register (address = 0xF2) [reset = 00000000]
      12. 8.5.12 Wireless Power Prop Packet Payload RAM Byte 2 Register (address = 0xF3) [reset = 00000000]
      13. 8.5.13 Wireless Power Prop Packet Payload RAM Byte 3 Register (address = 0xF4) [reset = 00000000]
      14. 8.5.14 RXID Readback Register (address = 0xF5 - 0xFA) [reset = see note]
9. 9 Application and Implementation
   1. 9.1 Application Information
   2. 9.2 Typical Applications
      1. 9.2.1 Dual Mode Design (WPC and PMA Compliant) Power Supply 5-V Output with 1-A Maximum Current
         1. 9.2.1.1 Design Requirements
         2. 9.2.1.2 Detailed Design Procedure
            1. 9.2.1.2.1  Output Voltage Set Point
            2. 9.2.1.2.2  Output and Rectifier Capacitors
               1. 9.2.1.2.2.1 TMEM
            3. 9.2.1.2.3  Maximum Output Current Set Point
            4. 9.2.1.2.4  TERM Resistor
            5. 9.2.1.2.5  Setting LPRB1 and LPRB2 Resistors
            6. 9.2.1.2.6  I2C
            7. 9.2.1.2.7  Communication Current Limit
            8. 9.2.1.2.8  Receiver Coil
            9. 9.2.1.2.9  Series and Parallel Resonant Capacitors
            10. 9.2.1.2.10 Communication, Boot and Clamp Capacitors
         3. 9.2.1.3 Application Curves
      2. 9.2.2 Embedded in System Board
      3. 9.2.3 bq51222 Implemented in Back Cover
10. 10Power Supply Recommendations
11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
12. 12器件和文档支持
    1. 12.1 器件支持
       1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
13. 13机械、封装和可订购信息