ZHCSED8 November 2015
PRODUCTION DATA.
7 Detailed Description
7.1 Overview
The bq76200 device is a low-power, high-side, N-Channel MOSFET driver for battery-pack protection systems, allowing a low-side battery-protection system to be implemented into a high-side protection system.
High-side charge/discharge FETs offer a huge advantage versus their low-side counterparts; with high-side implementation, a system-side processor can always communicate with the monitor or micro-controller (MCU) within the battery pack, regardless of whether the FETs are on or off — this is not easily supported in a low-side switching architecture due to the lack of a shared ground reference. One key benefit of an ever-present communication link is the ability to read out critical pack parameters despite safety faults, thereby enabling the system to assess pack conditions before determining if normal operation may resume.
The device allows independent control on charging and discharge via the digital enable pins. The device has integrated charge pump which is enabled by the CP_EN pin. The enable inputs, CHG_EN, DSG_EN, and PCHG_EN control the CHG, DSG, and PCHG FET gate drivers, respectively. The enable inputs can be connected to low-side FET driver outputs of an Analog Front End (AFE) such as Texas Instruments bq769x0 series, a general purpose microcontroller, or dedicated battery pack controller such as the bq783xx series.
In normal mode, the AFE or MCU enables the CHG_EN and DSG_EN, turning on the CHG and DSG FET drivers to connect the battery power to the PACK+ terminal. When a fault is detected by the AFE or the microcontroller, it can disable the CHG_EN and/or DSG_EN to open the charge or discharge path for protection. Note that when either the CHG_EN or DSG_EN is enabled, the charge pump will be automatically enabled even if the CP_EN is in the disable state. It is recommended to enable the charge pump via CP_EN pin during system start-up to avoid adding the tCPON time into the FET switching time during normal operation.
A lower charging current is usually applied to a deeply depleted battery pack. The bq76200 PCHG_EN input provides an option to implement a P-Channel MOSFET pre-charge path (current-limited path) in the battery pack.
An AFE usually provides individual cell voltages and/or battery stack voltage measurements, but it is not necessary to have PACK+ voltage measurement. The bq76200 PMON_EN pin, when enabled, will connect the PACK+ voltage onto the PACKDIV pin, which is connected to an external resistor divider to scale down the PACK+ voltage. This scaled down PACK+ voltage can be connected to a microcontroller's ADC input for voltage measurement. The system can use this information for charger detection or to implement advanced charging control.
For safety purposes, all the enable inputs are internally pulled down. If the AFE or microcontroller is turned off, or if the PCB trace is damaged, the internal pull down of the enable inputs will keep CHG, DSG, PCHG in an off state and the PACK+ voltage does not switch onto the PACKDIV pin.
7.2 Functional Block Diagram
Figure 7. Functional Block Diagram
7.3 Feature Description
7.3.1 Charge Pump Control
The bq76200 device has an integrated charge pump. A minimum of 470-nF capacitor is required on the V(VDDCP) pin to the BAT pin to ensure proper function of the charge pump. If the V(VDDCP) capacitor is disconnected, a residual voltage could reside at the CHG and/or DSG output if CHG_EN and/or DSG_EN are enabled. Such a fault condition can put the external FETs in high Rdson state and result in FET damage.
The V(VDDCP) capacitor can be scaled up to support more FETs in parallel (such as high-total FET-gate capacitance) than the value specified in the electrical characteristics table. A higher VDDCP capacitance results in longer tCPON time. See the Application Information section for more information. Note that probing the VDDCP pin may increase the loading on the charge pump and result in lower measurement value than the V(VDDCP) specification. Using higher impedance probe can reduce such effect on the measurement.
The charge pump is controlled by CP_EN and also OR'ed with the CHG_EN and DSG_EN inputs. This means by enabling CHG_EN or DSG_EN alone, the charge pump will automatically turn on even if the CP_EN pin is disabled. The PCHG_EN controls the PCHG pin, which is a P-channel FET driver and does not require the function of the charge pump. The charge pump is turned off by default. When CP_EN is high, the charge pump turns on regardless of the status of the CHG_EN and DSG_EN inputs.
When CP_EN is enabled, the charge pump voltage starts to ramp up. Once the voltage is above an internal UVLO level, about 9-V typical above VBAT, the charge pump is considered on. The charge pump voltage should continuously ramp to the V(VDDCP) level. If the CHG_EN and/or DSG_EN is enabled, the CHG and/or DSG voltage will starts to turn on after the charge pump voltage is above the UVLO level, and ramp up along the charge pump voltage to the V(VDDCP) level. Otherwise, the CHG and DSG do not turn on if the charge pump voltage fails to ramp up above UVLO. For example, if the C(VDDCP) is not scaled properly to support the number of FETs in parallel, the heavy loading would prevent the charge pump to ramp up above UVLO. CHG and DSG would not be turned on in this case.
When CHG_EN and/or DSG_EN is enabled after the charge pump is fully turned on, the CHG_EN-enable to CHG-on delay (or DSG_EN-enable to DSG-on delay) is simply the sum of (tprop + FET rise time). A system configuration example for this scenario will be connecting the CP_EN to the host MCU, enable CP_EN at system start-up and keep the CP_EN enabled during normal operation. This is the recommended configuration, because the charge pump ramp-up time, tCPON, becomes part of the system start-up time and does not add onto the FET switch delay during normal operation.
If CP_EN is not used (it is highly recommended to connect the CP_EN to ground), the charge pump on- and off-state is controlled by CHG_EN or DSG_EN. The CHG or DSG output will only be on after the charge-pump voltage is ramped up above UVLO. This means the CHG_EN-enable to CHG-on delay (or DSG_EN-enable to DSG-on delay) will be (tCPON + tprop + FET rise time).
The charge pump is turned off when CP_EN AND CHG_EN AND DSG_EN signals are all low. The charge pump is not actively driven low and the voltage on the V(VDDCP) capacitor bleeds off passively. If any of the CP_EN, CHG_EN, or DSG_EN signals is switched high again while the V(VDDCP) capacitor is still bleeding off its charge, the charge pump start up time, tCPON, will be shorter.
7.3.2 Pin Enable Controls
The bq76200 has four digital enable inputs that control the state of associated output signals as defined in the following table. The VIH and VIL levels of these enable pins are low enough to work with most MCUs. At the same times, the pins have high enough tolerant to allow direct control from an AFE FET driver. This gives system maker a flexible option to architect the battery pack configuration.
| INPUT PIN | ASSOCIATED OUTPUT PIN | DESCRIPTION |
|---|---|---|
| CHG_EN | CHG | Charge FET control |
| DSG_EN | DSG | Discharge FET control |
| PCHG_EN | PCHG | Pre-charge FET control |
| PMON_EN | PACKDIV | Pack monitor control |
7.3.2.1 External Control of CHG and DSG Output Drivers
The CHG_EN and DSG_EN pins provide direct control of the CHG and DSG FET driver. Table 1 summarizes the CHG and DSG statute with respect to the CP_EN, CHG_EN and DSG_EN inputs.
Table 1. CHG and DSG with Respect to CP_EN, CHG_EN, and DSG_EN
| CP_EN | CHG_EN | DSG_EN | CHARGE PUMP | CHG | DSG |
|---|---|---|---|---|---|
| Lo (default) | Lo (default) | Lo (default) | OFF (default) | OFF (default) | OFF (default) |
| Lo | Lo | Hi | ON | OFF | ON |
| Lo | Hi | Lo | ON | ON | OFF |
| Lo | Hi | Hi | ON | ON | ON |
| Hi | Lo | Lo | ON | OFF | OFF |
| Hi | Lo | Hi | ON | OFF | ON |
| Hi | Hi | Lo | ON | ON | OFF |
| Hi | Hi | Hi | ON | ON | ON |
7.3.2.2 External Control of PCHG Output Driver
The PCHG output driver is designed to drive a P-channel FET and is controlled by the PCHG_EN pin. The PCHG driver provides an option to implement a separate charging path with a P-channel FET to charge the battery when the cells are deeply depleted. A resistor should be added in series to the P-channel pre-charge FET to limit the charging current. A pre-charge current is usually at or less than 1/20 of the normal charge current if the charger does not support lower current pre-charge. Refer to the battery cell specification from the cell manufacturer charging for the appropriate current limit.
| PCHG_EN | PCHG |
|---|---|
| Lo (default) | OFF (default) |
| Hi | ON |
7.3.2.3 Pack Monitor Enable
The bq76200 device provides an internal-switch control to post the PACK+ voltage on to the PACKDIV pin. A resistor divider can be connected to the PACKDIV pin externally to divide down the PACK+ voltage into a measurable range of an MCU. The PMON_EN controls the internal switch between PACK pin and PACKDIV pin. The internal switch has an on resistance of R(PMONFET). The external resistor divider for PACKDIV pin should be selected to avoid exceeding the absolute maximum of the PACKDIV pin and should also keep the loading current < 500 µA. If this function is not used, the PACKDIV pin should leave floating. To reduce power consumption, the PMON_EN should be enabled only when PACK+ voltage measurement is needed.
| PMON_EN | PACKDIV |
|---|---|
| Lo (default) | DISABLED (default) |
| Hi | ENABLED |
7.4 Device Functional Modes
- In NORMAL mode, the bq76200 charge pump is turned on by enabling either CP_EN, CHG_EN, or DSG_EN. In this mode, typically the CHG and DSG outputs are driven to V(BAT) + V(VDDCP).
- In SHUTDOWN mode, the bq76200 is completely powered down. When CHG_EN, DSG_EN, and CP_EN are driven low, the device enters SHUTDOWN mode, and the outputs are driven low.
| DEVICE MODES | CONDITION |
|---|---|
| NORMAL | CHG_EN = Hi, DSG_EN = Hi, CP_EN = Hi, PCHG_EN = don't care, PMON_EN = don't care |
| SHUTDOWN | CHG_EN = Lo, DSG_EN = Lo, CP_EN = Lo, PCHG_EN = Lo, PMON_EN = Lo |