ZHCSVT2A April   2022  – April 2024 BQ76922

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76922
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 Voltage References
    14. 6.14 Coulomb Counter
    15. 6.15 Coulomb Counter Digital Filter (CC1)
    16. 6.16 Current Measurement Digital Filter (CC2)
    17. 6.17 Current Wake Detector
    18. 6.18 Analog-to-Digital Converter
    19. 6.19 Cell Balancing
    20. 6.20 Cell Open Wire Detector
    21. 6.21 Internal Temperature Sensor
    22. 6.22 Thermistor Measurement
    23. 6.23 Internal Oscillators
    24. 6.24 High-side NFET Drivers
    25. 6.25 Comparator-Based Protection Subsystem
    26. 6.26 Timing Requirements – I2C Interface, 100kHz Mode
    27. 6.27 Timing Requirements – I2C Interface, 400kHz Mode
    28. 6.28 Timing Requirements – HDQ Interface
    29. 6.29 Interface Timing Diagrams
    30. 6.30 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Using VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Voltage Calibration (ADC Measurements)
      9. 7.5.9  Voltage Calibration (COV and CUV Protections)
      10. 7.5.10 Current Calibration
      11. 7.5.11 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 LDO Control
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  Fuse Drive
      10. 7.7.10 Cell Open Wire
      11. 7.7.11 Low Frequency Oscillator
      12. 7.7.12 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
  10. 9 Power Supply Requirements
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 Documentation Support
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSN|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.24 High-side NFET Drivers

Typical values stated where TA = 25°C and VBAT = 18.5 V, min/max values stated where TA = -40°C to 85°C and VBAT = 4.7 V to 27.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(FETON_HI) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ VBAT ≤ 27.5 V, VLD ≤ VDSG(1) CHG/DSG CL = 20 nF, charge pump high overdrive setting 10 11 13 V
V(FETON_HI_LOBAT) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ VBAT < 8 V, VLD ≤ VDSG(1) CHG/DSG CL = 20 nF, charge pump high overdrive setting 8 11 13 V
V(FETON_LO) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 8 V ≤ VBAT ≤ 27.5 V, VLD ≤ VDSG(1) CHG/DSG CL = 20 nF, charge pump low overdrive setting 4.5 5.7 7 V
V(FETON_LO_LOBAT) CHG pin voltage with respect to BAT, DSG pin voltage with respect to BAT, 4.7 V ≤ VBAT < 8 V, VLD ≤ VDSG(1) CHG/DSG CL = 20 nF, charge pump low overdrive setting 3.5 5 7 V
V(SRCFOL_FETON) DSG on voltage with respect to BAT CHG/DSG CL = 20 nF, source follower mode 0 V
V(CHGFETOFF) CHG off voltage with respect to BAT CHG/DSG CL = 20 nF, steady state value 0.4 V
V(DSGFETOFF) DSG off voltage with respect to LD CHG/DSG CL = 20 nF, steady state value 0.7 V
t(FET_ON) CHG and DSG rise time CHG/DSG CL = 20 nF, RGATE = 100 Ω, 0.5 V to 4 V gate-source overdrive, charge pump mode(3)(4) 21 40 µs
t(CHGFETOFF) CHG fall time to BAT CHG CL = 20 nF, RGATE = 100 Ω, 90% to 10% of V(FETON)(4) 46 65 µs
t(DSGFETOFF) DSG fall time to LD DSG CL = 20 nF, RGATE = 100 Ω, 90% to 10% of V(FETON)(4) 2 20 µs
t(CP_START) Charge pump start up time(2) CL = 20 nF, C(CP1) = 470 nF, 10% to 90% of V(FETON) 100 ms
C(CP1) Charge pump capacitor(2) 100 470 2200 nF
(1) When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that VLD > VDSG, the voltage at DSG will rise to ≈ VLD - 0.7 V
(2) Specified by design
(3) Specified by characterization
(4) RGATE can be optimized during design and system evaluation for best performance.  A larger value may be desired to avoid an overly fast FET turn off, which can result in a large voltage transient due to cell and harness inductance.
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