米6体育平台手机版

ZHCS327D July 2011 – October 2016

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PW|20
- MPDS362A
RGE|24
- MPQF124G

散热焊盘机械数据 (封装 | 引脚)

RGE|24
- QFND008AA

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
V_BAT	Supply voltage	BAT	–0.3	36	V
V_I	Input voltage	Cell input differential, VCn to VCn+1, n = 0 to 5	–0.3	9	V
		Cell input, VCn, n = 1 to 6	–0.3	(6 × n)
		BAT to VC6 differential	–10	10
		VC0 ⁽²⁾	–3	3
		SENSEP, SENSEN	–3	3
		SCL, SDA	–0.3	6
V_O	Output voltage	VCOUT, VIOUT, VREF	–0.3	3.6	V
		VTB, V3P3	–0.3	7
		ALERT	–0.3	30
		VCTL	–0.3	36
I_CB	Cell balancing current			70	mA
I_IN	Cell input current		–25	70	mA
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Negative voltage swings on VC0 in the absolute maximum range can cause unwanted circuit behavior and should be avoided.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions⁽¹⁾

				MIN	NOM	MAX	UNIT
	Supply voltage	BAT		4.2		26.4	V
V_I	Input voltage	Cell input differential, VCn to VCn+1, n = 0 to 5		1.4		4.4	V
		Cell input, VCn, n = 1 to 6				4.4 × n	V
		BAT to VC6 differential		–8		8	V
		VC0, SENSEN			0		V
		SENSEP		–125		375	mV
		SCL, SDA		0		5.5	V
		V3P3	Backfeeding⁽²⁾			5.5	V
		ALERT	Wakeup function	0		26.4	V
V_O	Output voltage	VCOUT, VIOUT		0		V3P3 + 0.2	V
		VREF	REFSEL = 0		1.5		V
		VREF	REFSEL = 1		3		V
		VTB				5.5	V
		V3P3	Regulating		3.3		V
		VCTL		0.8		26.4	V
		ALERT	Alert function	0		5.5	V
I_CB	Cell balancing current			0		50	mA
T_A	Operating free-air temperature			–25		85	°C
T_FUNC	Functional free-air temperature			–40		100	°C

(1) All voltages are relative to VSS, except “Cell input differential.”

(2) Internal 3.3-V regulator may be overridden (that is, backfed) by applying an external voltage larger than the regulator voltage.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		bq76925		UNIT
		PW (TSSOP)	RGE (VQFN)
		20 PINS	24 PINS
R_θJA	Junction-to-ambient thermal resistance	97.5	36	°C/W
R_{θJC (top)}	Junction-to-case (top) thermal resistance	31.7	38.6	°C/W
R_θJB	Junction-to-board thermal resistance	48.4	14	°C/W
ψ_JT	Junction-to-top characterization parameter	1.5	0.6	°C/W
ψ_JB	Junction-to-board characterization parameter	47.9	14	°C/W
R_{θJC (bot)}	Junction-to-case (bottom) thermal resistance	n/a	4.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics: Supply Current

BAT = 4.2 to 26.4 V, VCn = 1.4 to 4.4, T_A = –25°C to +85°C
Typical values stated where T_A = 25°C and BAT= 21.6 V (unless otherwise noted)

PARAMETER		TEST CONDITION		TYP	MAX	UNIT
I_DD1	Normal mode supply current	All device functions enabled All pins unloaded SDA and SCL high		40	48	µA
I_DD2	Standby mode 1 supply current	V3P3 and overcurrent monitor enabled All pins unloaded All other device functions disabled SDA and SCL high		14	17	µA
I_DD3	Standby mode 2 supply current	V3P3 enabled All pins unloaded All device functions disabled SDA and SCL high		12	14	V
I_DD4	Sleep mode supply current	V3P3 disabled All pins unloaded All device functions disabled SDA and SCL low		1	1.5	µA
I_VCn	Input current for selected cell	All cell voltages equal Cell balancing disabled Open cell detection disabled during cell voltage monitoring	n = 6	2.4	2.7	µA
			n = 1 – 5		< 0.5
			n = 1 – 5 at 25°C		< 0.3
∆I_VCn	Cell to cell input current difference	All cell voltages equal Cell balancing disabled Open cell detection disabled			< 0.2	µA

7.6 Internal Power Control (Startup and Shutdown)

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
V_POR	Power on reset voltage	Measured at BAT pin	Initial BAT < 1.4 VBAT rising⁽¹⁾	4.3	4.5	4.7	V
V_POR	Power on reset voltage	Measured at BAT pin	Initial BAT > 1.4 VBAT rising⁽¹⁾	6.5	7	7.5	V
V_SHUT	Shutdown voltage⁽²⁾	Measured at BAT pin, BAT falling				3.6	V
t_POR	Time delay after POR before I2C comms allowed	CV3P3 = 4.7 µF				1	ms
V_WAKE	Wakeup voltage	Measured at ALERT pin		0.8		2	V
t_{WAKE_PLS}	Wakeup signal pulse width			1		5	μs
t_{WAKE_DLY}	Time delay after wakeup before I2C comms allowed	CV3P3 = 4.7 µF				1	ms

(1) Initial power up will start with BAT < 1.4 V, however if BAT falls below V_SHUT after rising above V_POR, the power on threshold depends on the minimum level reached by BAT after falling below V_SHUT.

(2) Following POR, the device will operate down to this voltage.

7.7 3.3-V Voltage Regulator

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
V_CTL	Regulator control voltage ⁽¹⁾⁽²⁾	Measured at VCTL, V3P3 regulating	3.3		26.4	V
V_V3P3	Regulator output	Measured at V3P3, I_REG = 0 to 4 mA, BAT = 4.2 to 26.4 V	3.2	3.3	3.4	V
I_REG	V3P3 output current				4	mA
I_SC	V3P3 short circuit current limit	V3P3 = 0.0 V	10		17	mA
V_TB	Thermistor bias voltage	Measured at VTB, I_TB = 0		V_V3P3		V
I_TB	Thermistor bias current				1	mA
R_TB	Thermistor bias internal resistance	R_DS(ON) for internal FET switch, I_TB = 1 mA		90	130	Ω

(1) When a bypass FET is used to supply the regulated 3.3 V load current, VCTL automatically adjusts to keep V3P3 = 3.3 V. Note that V_CTL,MIN and the FET V_GS will determine the minimum BAT voltage at which the bypass FET will operate.

(2) If VCTL is tied to BAT, the load current is supplied through V3P3.

7.8 Voltage Reference

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
V_REF	Voltage reference output	Before gain correction, T_A = 25°C	REF_SEL = 0	1.44		1.56	V
		Before gain correction, T_A = 25°C	REF_SEL = 1	2.88		3.12
		After gain correction, ⁽¹⁾ T_A = 25°C	REF_SEL = 0	–0.1%	1.5	+0.1%
		After gain correction, ⁽¹⁾ T_A = 25°C	REF_SEL = 1	–0.1%	3	+0.1%
V_{REF_CAL}	Reference calibration voltage	Measured at VCOUT	VCOUT_SEL = 2	–0.9%	0.5 × V_REF	+0.9%	V
			VCOUT_SEL = 3	–0.5%	0.85 × V_REF	+0.5%	V
			(0.85 × V_REF) – (0.5 × V_REF)	–0.3%	0.35 × V_REF	+0.3%	V
∆V_REF	Voltage reference tolerance	T_A = 0 – 50°C		–40		40	ppm/°C
I_REF	VREF output current					10	µA

(1) Gain correction factor determined at final test and stored in non-volatile storage. Gain correction is applied by Host controller.

7.9 Cell Voltage Amplifier

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
G_VCOUT	Cell voltage amplifier gain	Measured from VCn to VCOUT	REF_SEL = 0	–1.6%	0.3	1.5%
G_VCOUT	Cell voltage amplifier gain	Measured from VCn to VCOUT	REF_SEL = 1	–1.6%	0.6	1.5%
O_VCOUT	Cell voltage amplifier offset	Measured from VCn to VCOUT		–16		15	mV
V_COUT	Cell voltage amp output range ⁽¹⁾	Measured at VCOUT, VCn = 5 V	REF_SEL = 0	1.47	1.5	1.53	V
		Measured at VCOUT, VCn = 5 V	REF_SEL = 1	2.94	3	3.06	V
		Measured at VCOUT, VCn = 0 V			0		V
∆V_COUT	Cell voltage amplifier accuracy	VCn = 1.4 V to 4.4 V, After correction, ⁽²⁾ Measured at VCOUT ⁽³⁾ REF_SEL = 1⁽⁴⁾	T_A = 25°C	–3		3	mV
			T_A = 0°C to 50°C	–5		5
			T_A = –25°C to +85°C	–8		8
I_VCOUT	VCOUT output current⁽⁵⁾					10	µA
t_VCOUT	Delay from VCn select to VCOUT	Output step of 200 mV, C_OUT = 0.1 µF				100	µs

(1) For VCn values greater than 5 V, VCOUT clamps at approximately V3P3.

(2) Correction factor determined at final test and stored in non-volatile storage. Correction is applied by Host controller.

(3) Output referred. Input referred accuracy is calculated as ∆V_COUT / G_VCOUT (for example, 3 / 0.6 = 5).

(4) Correction factors are calibrated for gain of 0.6. Tolerance at gain of 0.3 is approximately doubled. Contact TI for information on devices calibrated to a gain of 0.3.

(5) Max DC load for specified accuracy.

7.10 Current Sense Amplifier

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
G_VIOUT	Current sense amplifier gain	Measured from SENSEN, SENSEP to VIOUT	I_GAIN = 0		4
G_VIOUT	Current sense amplifier gain	Measured from SENSEN, SENSEP to VIOUT	I_GAIN = 1		8
V_IIN	Current sense amp input range	Measured from SENSEN, SENSEP to VSS		–125		375	mV
V_IOUT	Current sense amp output range	Measured at VIOUT	REF_SEL = 0	0.25		1.25	V
	Current sense amp output range	Measured at VIOUT	REF_SEL = 1	0.5		2.5	V
	Zero current output	Measured at VIOUT SENSEP = SENSEN	REF_SEL = 0		1		V
	Zero current output	Measured at VIOUT SENSEP = SENSEN	REF_SEL = 1		2		V
∆V_IOUT	Current amplifier accuracy			–1%		1%
IV_IOUT	VIOUT output current ⁽¹⁾					10	µA

(1) Max DC load for specified accuracy

7.11 Overcurrent Comparator

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
V_{BAT_COMP}	Minimum VBAT for comparator operation⁽¹⁾				5	V
G_VCOMP	Comparator amplifier gain	Measured from SENSEP to comparator input		1
V_ITRIP	Current comparator trip threshold⁽²⁾		25		400	mV
∆V_ITRIP	Current comparator accuracy	V_ITRIP = 25 mV	–6		6	mV
∆V_ITRIP	Current comparator accuracy	V_ITRIP > 25 mV	–10%		10%	V
V_{OL_ALERT}	ALERT Output Low Logic	I_ALERT = 1 mA			0.4	V
V_{OH_ALERT}	ALERT Output High Logic ⁽³⁾		NA	NA	NA
I_ALERT	ALERT Pulldown current	ALERT = 0.4 V, Output driving low	1			mA
I_{ALERT_LKG}	ALERT Leakage current	ALERT = 5 V, Output Hi-Z			< 1	μA
t_OC	Comparator response time				100	µs

(1) The Overcurrent Comparator is not guaranteed to work when VBAT is below this voltage.

(2) Trip threshold selectable from 25, 50, 75, 100, 125, 150, 175, 200, 225, 250, 275, 300, 325, 350, 375 or 400 mV.

(3) This parameter NA because output is open drain.

7.12 Internal Temperature Measurement

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
V_{TEMP_INT}	Internal temperature voltage	Measured at VCOUT, T_INT = 25°C	1.15	1.2	1.25	V
∆V_{TEMP_INT}	Internal temperature voltage sensitivity			–4.4		mV/°C

7.13 Cell Balancing and Open Cell Detection

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
R_BAL	Cell balancing internal resistance⁽¹⁾	R_DS(ON) for VC1 internal FET switch, VCn = 3.6 V	1	3	5	Ω
R_BAL	Cell balancing internal resistance⁽¹⁾	R_DS(ON) for internal VC2 to VC6 FET switch, VCn = 3.6 V	3	5.5	8	Ω

(1) Balancing current is not internally limited. The cell balancing operation is completely controlled by the Host processor, no automatic function or time-out is included in the part. Take care to ensure that balancing current through the part is below the maximum power dissipation limit. The Host algorithm is responsible for limiting thermal dissipation to package ratings.

7.14 I²C Compatible Interface

PARAMETERS			MIN	TYP	MAX	UNIT
DC PARAMETERS
V_IL	Input Low Logic Threshold				0.6	V
V_IH	Input High Logic Threshold		2.8			V
V_OL	Output Low Logic Drive	I_OL = 1 mA			0.20	V
V_OL	Output Low Logic Drive	I_OL = 2.5 mA			0.40	V
V_OH	Output High Logic Drive (Not applicable due to open-drain outputs)			N/A	V
I_LKG	I²C Pin Leakage	Pin = 5 V, Output in Hi-Z			< 1	µA
AC PARAMETERS
t_r	SCL, SDA　Rise Time				1000	ns
t_f	SCL, SDA　Fall Time				300	ns
t_w(H)	SCL Pulse Width High		4			µs
t_w(L)	SCL Pulse Width Low		4.7			µs
t_su(STA)	Setup time for START condition		4.7			µs
t_h(STA)	START condition hold time after which first clock pulse is generated		4			µs
t_su(DAT)	Data setup time		250			ns
t_h(DAT)	Data hold time		0⁽¹⁾			µs
t_su(STOP)	Setup time for STOP condition		4			µs
t_su(BUF)	Time the bus must be free before new transmission can start		4.7			µs
t _V	Clock Low to Data Out Valid				900	ns
t_h(CH)	Data Out Hold Time After Clock Low		0			ns
f_SCL	Clock Frequency		0		100	kHz
t_WAKE	I²C ready after transition to Wake Mode				2.5	ms