A load detection circuit is present on the CHG pin and activated whenever the CHG FET is disabled ([CHG_ON] = 0). This circuit detects if the CHG pin is externally pulled high when the high impedance (approximately 1 MΩ) pull-down path should actually be holding the CHG pin to VSS, and is useful for determining if the PACK– pin (outside of the AFE) is being held at a high voltage—for example, if the load is present while the power FETs are off. The state of the load detection circuit is read from the [LOAD_PRESENT] bit of the SYS_CTRL1 register.

After an OCD or SCD fault has occurred, the DSG FET will be disabled ([DSG_ON] cleared), and the CHG FET must similarly be explicitly disabled to activate the load detection circuit. The host microcontroller may periodically poll the [LOAD_PRESENT] bit to determine the state of the PACK– pin and determine when the load is removed ([LOAD_PRESENT] = 0).