ZHCSCE2I October 2013 – March 2022 BQ76920 , BQ76930 , BQ76940
PRODMIX
The ALERT pin serves as an active high digital interrupt signal that can be connected to a GPIO port of the host microcontroller. This signal is an OR of all bits in the SYS_STAT register.
In order to clear the ALERT signal, the source bit in the SYS_STAT register must first be cleared by writing a “1” to that bit. This will cause an automatic clear of the ALERT pin once all bits are cleared.
The ALERT pin may also be driven by an external source; for example, the pack may include a secondary overvoltage protector IC. When the ALERT pin is forced high externally while low, the device will recognize this as an OVRD_ALERT fault and set the [OVRD_ALERT] bit. This triggers automatic disabling of both CHG and DSG FET drivers. The device cannot recognize the ALERT signal input high when it is already forcing the ALERT signal high from another condition.
The ALERT pin has no internal debounce support so care should be taken to protect the pin from noise or other parasitic transients.
It is highly recommended to place an external 500 kΩ–1 MΩ pull-down resistor from ALERT to VSS as close to the IC as possible. Additional recommendations are:
a) To keep all traces between the IC and components connected to the ALERT pin very short.
b) To include a guard ring around the components connected to the ALERT pin and the pin itself.