米6体育平台手机版

ZHCSM58B January 2020 – November 2021 BQ76952

PRODUCTION DATA

1 特性
2 应用
3 说明
4 Revision History
5 Device Comparison Table
6 Pin Configuration and Functions
7 Specifications
1. 7.1 Absolute Maximum Ratings
2. 7.2 ESD Ratings
3. 7.3 Recommended Operating Conditions
4. 7.4 Thermal Information BQ76952
5. 7.5 Supply Current
6. 7.6 Digital I/O
7. 7.7 LD Pin
8. 7.8 Precharge (PCHG) and Predischarge (PDSG) FET Drive
9. 7.9 FUSE Pin Functionality
10. 7.10 REG18 LDO
11. 7.11 REG0 Pre-regulator
12. 7.12 REG1 LDO
13. 7.13 REG2 LDO
14. 7.14 Voltage References
15. 7.15 Coulomb Counter
16. 7.16 Coulomb Counter Digital Filter (CC1)
17. 7.17 Current Measurement Digital Filter (CC2)
18. 7.18 Current Wake Detector
19. 7.19 Analog-to-Digital Converter
20. 7.20 Cell Balancing
21. 7.21 Cell Open Wire Detector
22. 7.22 Internal Temperature Sensor
23. 7.23 Thermistor Measurement
24. 7.24 Internal Oscillators
25. 7.25 High-side NFET Drivers
26. 7.26 Comparator-Based Protection Subsystem
27. 7.27 Timing Requirements - I2C Interface, 100kHz Mode
28. 7.28 Timing Requirements - I2C Interface, 400kHz Mode
29. 7.29 Timing Requirements - HDQ Interface
30. 7.30 Timing Requirements - SPI Interface
31. 7.31 Interface Timing Diagrams
32. 7.32 Typical Characteristics
8 Device Description
1. 8.1 Overview
2. 8.2 Functional Block Diagram
3. 8.3 BQ76952 Device Versions
4. 8.4 Diagnostics
9 Device Configuration
1. 9.1 Commands and Subcommands
2. 9.2 Configuration Using OTP or Registers
3. 9.3 Device Security
4. 9.4 Scratchpad Memory
10Measurement Subsystem
1. 10.1 Voltage Measurement
2. 10.2 General Purpose ADCIN Functionality
3. 10.3 Coulomb Counter and Digital Filters
4. 10.4 Synchronized Voltage and Current Measurement
5. 10.5 Internal Temperature Measurement
6. 10.6 Thermistor Temperature Measurement
7. 10.7 Factory Trim of Voltage ADC
8. 10.8 Voltage Calibration (ADC Measurements)
9. 10.9 Voltage Calibration (COV and CUV Protections)
10. 10.10 Current Calibration
11. 10.11 Temperature Calibration
11Primary and Secondary Protection Subsystems
1. 11.1 Protections Overview
2. 11.2 Primary Protections
3. 11.3 Secondary Protections
4. 11.4 High-Side NFET Drivers
5. 11.5 Protection FETs Configuration and Control
  1. 11.5.1 FET Configuration
  2. 11.5.2 PRECHARGE and PREDISCHARGE Modes
6. 11.6 Load Detect Functionality
12Device Hardware Features
1. 12.1 Voltage References
2. 12.2 ADC Multiplexer
3. 12.3 LDOs
  1. 12.3.1 Preregulator Control
  2. 12.3.2 REG1 and REG2 LDO Controls
4. 12.4 Standalone Versus Host Interface
5. 12.5 Multifunction Pin Controls
6. 12.6 RST_SHUT Pin Operation
7. 12.7 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
8. 12.8 ALERT Pin Operation
9. 12.9 DDSG and DCHG Pin Operation
10. 12.10 Fuse Drive
11. 12.11 Cell Open Wire
12. 12.12 Low Frequency Oscillator
13. 12.13 High Frequency Oscillator
13Device Functional Modes
1. 13.1 Overview
2. 13.2 NORMAL Mode
3. 13.3 SLEEP Mode
4. 13.4 DEEPSLEEP Mode
5. 13.5 SHUTDOWN Mode
6. 13.6 CONFIG_UPDATE Mode
14Serial Communications Interface
1. 14.1 Serial Communications Overview
2. 14.2 I2C Communications
3. 14.3 SPI Communications
  1. 14.3.1 SPI Protocol
4. 14.4 HDQ Communications
15Cell Balancing
1. 15.1 Cell Balancing Overview
16Application and Implementation
1. 16.1 Application Information
2. 16.2 Typical Applications
3. 16.3 Random Cell Connection Support
4. 16.4 Startup Timing
5. 16.5 FET Driver Turn-Off
6. 16.6 Unused Pins
17Power Supply Requirements
18Layout
1. 18.1 Layout Guidelines
2. 18.2 Layout Example
19Device and Documentation Support
1. 19.1 Documentation Support
2. 19.2 支持资源
3. 19.3 Trademarks
4. 19.4 Electrostatic Discharge Caution
5. 19.5 术语表
20Mechanical, Packaging, Orderable Information

封装选项

机械数据 (封装 | 引脚)

PFB|48
- MTQF019B

散热焊盘机械数据 (封装 | 引脚)

订购信息

14.4 HDQ Communications

The HDQ interface is an asynchronous return-to-one protocol where a processor communicates with the BQ76952 device using a single-wire connection to the ALERT pin or the HDQ pin, depending on the configuration. The controller (host device) and the responder (the BQ76952 device) drive the HDQ interface using an open-drain driver with a pullup resistor from the HDQ interface to a supply voltage required on the circuit board. The BQ76952 device can be changed from the default communication mode to HDQ communication mode by setting the Settings:Configuration:Comm Type configuration register or by sending a subcommand (at which point the device switches to HDQ mode immediately).

Note: The SWAP_COMM_MODE() subcommand immediately changes the communications interface to that selected by the Comm Type configuration, while the SWAP_TO_HDQ() subcommand immediately changes the interface to HDQ using the ALERT pin.

With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted first.

The 8-bit command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB Bit 7). The R/W field directs the device to do one of the following:

Accept the next 8 bits as data from the host to the device or
Output 8 bits of data from the device to the host in response to the 7-bit command.

The HDQ peripheral on the BQ76952 device can transmit and receive data as an HDQ responder only.

The return-to-one data bit frame of HDQ consists of the following sections:

The first section is used to start the transmission by the host sending a Break (the host drives the HDQ interface to a logic-low state for a time t_(B)) followed by a Break Recovery (the host releases the HDQ interface for a time t_(BR)).
The next section is for host command transmission, where the host transmits 8 bits by driving the HDQ interface for 8 T_(CYCH) time slots. For each time slot, the HDQ line is driven low for a time T_(HW0) (host writing a "0") or T_(HW1) (host writing a "1"). The HDQ pin is then released and remains high to complete each T_(CYCH) time slot.
The next section is for data transmission where the host (if a write was initiated) or device (if a read was initiated) transmits 8 bits by driving the HDQ interface for 8 T_(CYCH) (if host is driving) or T_(CYCD) (if device is driving) time slots. The HDQ line is driven low for a time T_(HW0) (host writing a "0"), T_(HW1) (host writing a "1"), T_(DW0) (device writing a "0"), or T_(DW1) (device writing a "1"). The HDQ pin is then released and remains high to complete the time slot. The HDQ interface does not auto-increment, so a separate transaction must be sent for each byte to be transferred.