8.5.1.5.2 Fault Masking
All of the possible faults in BQ79606A-Q1 may be masked by the host by setting the corresponding MASK bit. When masked, the FAULT_SUMMARY register does not reflect the bit being set. Additionally, the NFAULT and FAULT* interface do NOT signal when the masked event occurs, however, the status register is updated. NFAULT deasserts once the mask bit is set for the case of an existing fault. Masking bits also prevents cell balancing from terminating when the fault occurs (if enabled). Masking of fault sources is controlled in the following registers:
- GPIO_FLT_MSK - Mask bits for GPIO_FAULT
- UV_FLT_MSK - Mask bits for UV_FAULT
- OV_FLT_MSK - Mask bits for OV_FAULT
- UT_FLT_MSK - Mask bits for UT_FAULT
- OT_FLT_MSK - Mask bits for OT_FAULT
- TONE_FLT_MSK - Mask bits for FAULTSTAT
- COMM_UART_FLT_MSK - Mask bits for COMM_UART_FAULT
- COMM_UART_RC_FLT_MSK - Mask bits for COMM_UART_RC_FAULT
- COMM_UART_RR_FLT_MSK- Mask bits for COMM_UART_RR_FAULT
- COMM_UART_TR_FLT_MSK- Mask bits for COMM_UART_TR_FAULT
- COMM_COMH_FLT_MSK - Mask bits for COMM_COMH_FAULT
- COMM_COMH_RR_FLT_MSK - Mask bits for COMM_COMH_RR_FAULT
- COMM_COMH_RC_FLT_MSK - Mask bits for COMM_COMH_RC_FAULT
- COMM_COMH_TR_FLT_MSK - Mask bits for COMM_COMH_TR_FAULT
- COMM_COML_FLT_MSK - Mask bits for COMM_UART_FAULT
- COMM_COML_RC_FLT_MSK - Mask bits for COMM_COML_RC_FAULT
- COMM_COML_RR_FLT_MSK - Mask bits for COMM_COML_RR_FAULT
- COMM_COML_TR_FLT_MSK - Mask bits for COMM_COML_TR_FAULT
- OTP_FLT_MSK - Mask bits for OTP_FAULT
- RAIL_FLT_MSK - Mask bits for RAIL_FAULT
- SYS_FLT1_MSK - Mask bits for SYS_FAULT1
- SYS_FLT2_MSK - Mask bits for SYS_FAULT2
- SYS_FLT3_MSK - Mask bits for SYS_FAULT3
- OVUV_BIST_FLT_MSK - Mask bits for OVUV_BIST_FAULT
- OTUT_BIST_FLT_MSK - Mask bits for OTUT_BIST_FAULT