8.5.1.8 Error Check and Correct (ECC) OTP

Register values for selected registers (0x0000 to 0x00C7) are permanently stored in OTP. All registers also exist as volatile storage locations at the same addresses, referred to as "shadow" registers. The volatile registers are for reading, writing, and device control. For a list of registers included in the OTP, see the Register Summary Table. During wakeup, the BQ79606A-Q1 first loads all shadow registers with hardware default values listed in the Register Summary. Then the BQ79606A-Q1 loads the registers conditionally with OTP contents from the results of the Error Check and Correct (ECC) evaluation of the OTP. The OTP is loaded to shadow registers in 64-bit blocks; each block has its own Error Check and Correct (ECC) value stored. The ECC detects a single-bit (Single-Error-Correction) or double-bit (Double-Error-Detection) changes in OTP stored data. The ECC is calculated for each block, individually. Single-bit errors are corrected, double-bit errors are only detected, not corrected. A block with good ECC is loaded. A block with a single-bit error is corrected, and the SYS_FAULT3[SEC_DET] bit is set to flag the corrected error event. Additionally, the SEC_BLK register is updated with the location of the error corrected block. This enables the host to keep track of potentially damaged memory. The block is loaded to shadow registers after the single-bit error correction. Since the evaluation is on a block-by-block basis, it is possible for multiple blocks to have a single-correctable error and still be loaded correctly. Multiple-bit errors can exist with full correction, as long as they are limited to a single error per block. A block with a bad ECC comparison (two-bit errors in one block) is not loaded and the SYS_FAULT3[DED_DET] bit is set to flag the failed bit-error event. Additionally, the DED_BLK register is updated with the block where the double error occurred. The hardware default value remains in the register. This allows some blocks to be loaded correctly (no fail or single-bit corrected value) and some blocks not to load. When either of the SYS_FAULT3[SEC_DET] or SYS_FAULT3[DED_DET] is set, and the condition is not cleared by a device reset (write CONTROL1[SOFT_RESET] or a WAKE command), the device is corrupted and must not be used.

The ECC engine uses the industry standard 72,64 SEC DEC ECC implementation. The OTP is protected by a (72, 64) Hamming code, providing single error correction, double error detection (SECDED). For each 64-bits of data stored in OTP, an additional 8-bits of parity information are stored. Therefore, the ECC code imposes an area overhead on the OTP of (72 – 64) / 64, or 12.5%. The parity bits are designated p0, p1, p2, p4, p8, p16, p32 and p64. Bit p0 covers the entire encoded 72- bit ECC block. The remaining seven parity bits are assigned according to the following rule:

1. Parity bit p1 covers odd bit positions, i.e. bit positions which have the least significant bit of the bit position equal to 1 (1, 3, 5, etc.), including the p1 bit itself (bit 1).

2. Parity bit p2 covers bit positions which have the second least significant bit of the bit position equal to 1 (2, 3, 6, 7, 10, 11, etc.), including the p2 bit itself (bit 2).

The pattern continues for p4, p8, p16, p32 and p64. Table below specifies the complete encoding.