9.2.1.2.13.3 GPIO Addressing

Prior to using the GPIO addressing function in a stack, all devices must be awake and ready for communication. The steps necessary for this state are detailed elsewhere in this document, but typically require a few milliseconds per device. Very simple "stacks" consisting of a single device may use address 0x00 (or any other valid address) for the device. The first device in stacks of more than one device may also use address 0x00. GPIO1 to GPIO6 are programmable to be addressing inputs using the GPIO*_CONF[ADD_SEL] bit. When fewer stack devices are used, fewer GPIOs are required for addressing. For example, if 10 device address are required, only GPIO1 through GPIO4 are required for addressing. The additional GPIOs are still available for the additional functionality. The GPIO number corresponds to the bit number in the DEV_ADD_STAT register (i.e. GPIO2 is bit 2). The GPIO is automatically setup as input when addressing is enabled (GPIO*_CONF[ADD_SEL]=1). GPIO*_CONF[GPIO_SEL] bit is ignored.

When CONFIG[GPIO_ADD_SEL] = 1 and CONTROL1[ADD_WRITE_EN] is set, the device enters GPIO addressing mode. In this mode, the device samples the enabled GPIO and updates the DEV_ADD_STAT[ADD] bits. Any GPIOs that do not have GPIO addressing mode enabled are read as '0'. At this time, the user may write to the DEVADD_OTP[ADD] bits to save the address, or the addressing may be done as part of the initialization process. Once the address is updated, the CONTROL1[ADD_WRITE_EN] bit is self cleared and the address is not writeable. It should be noted that once the GPIOs are used for the addressing, they may be reconfigured to be used in a different function without affecting the addressing. To GPIO-address the stack of BQ79606A-Q1 devices, use the following procedure

1. Configure the addressing GPIOs in hardware to the required address. The addressing must be sequential from the first to the last device
2. Broadcast write to the GPIO*_CONF[ADD_SEL] bits to enable the required addressing GPIOs
3. Broadcast write CONFIG[GPIO_ADD_SEL] = 1 (if not already set by OTP default)
4. Broadcast write CONTROL1[ADD_WRITE_EN] = 1
5. Set the CONFIG[STACK_DEV] register bit as base for base device and as stack for stack devices.
6. Single device write to the top device in the stack to set the CONFIG[TOP_STACK] bit and update CRC for that device

Good practice dictates that all devices be checked by reading back their address registers, at a minimum, to establish that the addressing functions worked properly. Subsequent reading and writing depend on correctly addressed devices in the stack or executing any user-initiated tests.