The SPI master has a loopback function that is enabled using the DIAG_COMM_CTRL[SPI_LOOPBACK] bit. When enabled, the byte in the SPI_TX* registers are clocked directly to the MISO pin of the SPI master to verify the SPI master functionality. This is performed internally, so no external connection is needed to run this test. This verifies that the SPI function is working correctly. The SPI_CFG, SPI_TX*, and SPI_EXE registers are written as a normal SPI transaction, but the external pins do not toggle during this mode. That is, the external pins stay static in their last state and do not change state during the loopback operation.

The expected result of the test is that the byte in the SPI_TX* register is read into the SPI_RX* register. The SS pin is latched to the setting in SPI_EXE[SS_CTRL] that existed when the LOOPBACK mode was enabled. The CPHA and CPOL parameters must be set before entering LOOPBACK mode to ensure proper operation. Changing the CPOL or CPHA parameters while in LOOPBACK mode may result in errant pulses on the SPI outputs and is not recommended.