The device implements a power supply BIST (Built-In Self-Test) function to test the primary power supply failure diagnostic paths that cover the following detections:

• FAULT_PWR1[AVDD_OV], [AVDD_OSC], [DVDD_OV], [CVDD_OV] and [CVDD_UV]
• FAULT_PWR2[TSREF_OV], [TSREF_UV] and [NEG5V_UV]

The power supply BIST is essentially a check on the checker and it is a command base function initiated by host.

The power supply BIST, once started, will force a fault on failure detection path on each supply. Take AVDD OV diagnostic path as an example, when the BIST engine tests the AVDD OV path, the following occur:

1. The BIST engine forces a fail to the AVDD OV comparator
2. The BIST engine then checks to ensure the signal to trigger FAULT register is asserted, and the signal to trigger NFAULT is also asserted
3. The BIST engine resets the FAULT register and NFAULT signal (that is, clears the FAULT_PWR1/2/3 registers and deasserts NFAULT)
4. The BIST engine repeats step 1 to step 3 on the next power supply diagnostic path check (for example, AVDD OSC) until all intended diagnostic paths covered by BIST are tested.

Start power supply BIST by sending DIAG_PWR_CTRL[PWR_BIST_GO] = 1. The BIST run will not abort even if a failure is detected during the run. At the end of the BIST run, the result is indicated by the FAULT_PWR2[PWRBIST_FAIL] flag.

The power supply BIST forces a failure and ensures the diagnostic path triggers the fault accordingly. A failure on the BIST run indicates a diagnostic path is unable to trigger in a fault condition. To further examine which path is unable to indicate a failure, host can set the DIAG_PWR_CTRL[BIST_NO_RST] = 1. This bit disables the reset step during the BIST run. Re-start power supply BIST with this option enabled. At the end of the BIST run, examine the FAULT_PWR1 and FAULT_PWR2 registers. Any register flag that remains 0 indicates it is unable to flag a failure.

Figure 8-39 Power Supply BIST