ZHCSTD7A December 2021 – November 2023 BQ79631-Q1
PRODUCTION DATA
The differential daisy-chain (vertical) interface uses an asynchronous 13-bit byte-transfer protocol. Data is transferred LSB first and every bit is duplicated (with a complement) to ensure the transmission has no DC content.
A byte starts with a Preamble, followed by two SYNC bits, a start-of-frame bit, eight data bits starting from the LSB D0 to MSB D7 (D0 is transmitted just after State-Of-Frame and D7 comes last before the Byte Error and Postamble).
The device extracts timing information using the Preamble and SYNC bits to decode the rest of the bit value in the byte. If any of the following errors is detected, the byte is not processed and register error bit is set.
Once the two valid SYNC bits are received, the additional bits are decoded and sent to the command processor. The device continues to detect any error on this byte, and if error is detected, the Byte Error (BERR) bit will be set in this byte. The DEBUG_COMH/L_BIT[PERR] = 1 depends on which COM port detects the error. The following condition will set the BERR bit in the byte.
In the meantime, each bit is still being retransmitted to the next device. If the device is unable to decode a 1 or a 0 for the bit, it will retransmit with 0 with the BERR bit set in the byte. When the new device detects the BERR bit is set to 1 in the receiving byte, it will ignore the questionable byte and set the DEBUG_COMH/L_BIT[BERR_TAG] = 1, indicating a byte is received with BERR. The questionable byte being ignored is likely to cause other communication errors and is likely to trigger the DEBUG_COMH/L_BIT[PERR] = 1 being set in the new device as well. The questionable byte continues to be retransmitted up the daisy-chain with BERR set and the process continues.
Bit Field | Description |
---|---|
Preamble (half-bit) | Indicates a start of transaction, signaling the receiver to start sampling. This half-bit and the following two SYNC bits are used to extra timing information. |
SYNC[1:0] | Always 0b00. The SYNC bits are used for the digital to assess the timing and noise level on the byte, improving the detection of a 1 and 0 in a noisy environment. |
Start-Of-Frame (1-bit) | The Start-Of-Frame (SOF) bit indicates the follow-on data byte is the initialization byte, a
start of a communication transaction frame. Stack device needs this
information to process the communication. For command frame transaction, the base device is responsible to set the SOF bit as it translates the UART communication to the daisy-chain communication. The initialization byte contains data size information. Based on the data size information, the base device would count the number of bytes received and set the next SOF bit accordingly. The UART COMM CLEAR signal resets the UART receiver which includes the frame handling of the logic. Hence, the next byte after COMM CLEAR must have SOF set to 1 because the COMM CLEAR indicates the system clears UART and re-starts the communication. |
Data[7:0] | The actual byte of the communication transaction frame |
Byte Error BERR (1-bit) | Indicates an error detected in this byte. When a device receives a byte with BERR set by the lower device, it will retransmit the byte also with BERR = 1. Because each data bit is re-clocked from one device to the next, the next device may not detect a communication error. However, the tag of the [BERR] bit would indicate this communication frame has an error during its previous transaction. |
Postamble (half-bit) | Indicates the end of transaction |
Each byte is transmitted at 2 MHz (250 ns per pulse or 500 ns per couplet). The time between each byte depends on the UART baud rate (1 Mbps in normal operation), but the byte time is always the same. The communication frame is defined with idle time between byte. In some rare cases, communication signal may not terminate cleanly, leaving ringing at the end of a byte. In such case, increasing the byte to byte gap can improve the communication robustness. The device allows additional byte gap insert between bytes in the response frame through STACK_RESPONSE register setting.