ZHCSTD7A December 2021 – November 2023 BQ79631-Q1
PRODUCTION DATA
| Address | 0x033E | |||||||
| RW | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
| Name | RSVD | PROT_BIST _NO_RST | ||||||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| RSVD = | Reserved | |||||||
| PROT_BIST_NO_RST = | Use for further diagnostic if the protector BIST detects a failure. When this bit is set to 1, the device will not clear the FAULT_OV1/2, FAULT_UV1/2, registers. The NFAULT signal will be latched once it is asserted. Note: Host ensures there is no fault before starting the BIST run with this bit set to 0. 0 = During BIST run, when the device asserts a fault to check the protector comparators and MUX and asserts the correct OV, UV fault bits the NFAULT pin. When this bit is 0, the device clears the fault and deasserts NFAULT before switching to the next channel. 1 = During BIST run, the fault created during the test will not be cleared before switching to next VS or GPIO channel. The NFAULT pin is latched once it is asserted. | |||||||