ECC:

Register values for selected registers (0x0000 to 0x002F) are permanently stored in OTP. All registers also exist as volatile storage locations at the same addresses, referred to as shadow registers. The volatile registers are for reading, writing, and device control. For a list of registers included in the OTP, see Section 8.5.1.

During wakeup, the device first loads all shadow registers with hardware default values listed in Section 8.5.1. Then the device loads the registers conditionally with OTP contents from the results of the Error Check and Correct (ECC) evaluation of the OTP. The OTP is loaded to shadow registers in 64-bit blocks; each block has its own Error Check and Correct (ECC) value stored. The ECC detects a single-bit (Single-Error-Correction) or double-bit (Double-Error-Detection) changes in OTP stored data. The ECC is calculated for each block, individually.

Single-bit errors are corrected, double-bit errors are only detected, not corrected. A block with good ECC is loaded. A block with a single-bit error is corrected, and the FAULT_OTP[SEC_DET] bit is set to flag the corrected error event. Additionally, the DEBUG_OTP_SEC_BLK register is updated with the location of the error corrected block. This enables the host to keep track of potentially damaged memory. The block is loaded to shadow registers after the single-bit error correction. Because the evaluation is on a block-by-block basis, it is possible for multiple blocks to have a single-correctable error and still be loaded correctly. Multiple-bit errors can exist with full correction, as long as they are limited to a single error per block.

A block with a bad ECC comparison (two-bit errors in one block) is not loaded and the FAULT_OTP[DED_DET] bit is set to flag the failed bit-error event. Additionally, the DEBUG_OTP_DED_BLK register is updated with the block where the double error occurred. The hardware default value remains in the register. This allows some blocks to be loaded correctly (no fail or single-bit corrected value) and some blocks not to load. When the FAULT_OTP[SEC_DET] or FAULT_OTP[DED_DET] bit is set and the condition is not cleared by a device reset, the device is corrupted and must not be used.

The ECC engine uses the industry standard 72,64 SEC DEC ECC implementation. The OTP is protected by a (72, 64) Hamming code, providing single error correction, double error detection (SECDED). For each 64 bits of data stored in OTP, an additional eight bits of parity information are stored. The parity bits are designated p0, p1, p2, p4, p8, p16, p32, and p64. Bit p0 covers the entire encoded 72-bit ECC block. The remaining seven parity bits are assigned according to the following rule:

• Parity bit p1 covers odd bit positions, that is, bit positions which have the least significant bit of the bit position equal to 1 (1, 3, 5, and so on), including the p1 bit itself (bit 1).
• Parity bit p2 covers bit positions which have the second least significant bit of the bit position equal to 1 (2, 3, 6, 7, 10, 11, and so on), including the p2 bit itself (bit 2).
• The pattern continues for p4, p8, p16, p32, and p64. Table 8-28 specifies the complete encoding.

ECC Diagnostic Test: The device provides a diagnostic tool to test the ECC function. There are two modes that are available to run the diagnostic. The first, auto mode (OTP_ECC_TEST[MANUAL_AUTO] = 0), uses internal data to run the tests. In auto mode, the OTP_ECC_TEST[DED_SEC] bit selects the type of test that is to be performed and the OTP_ECC_TEST[ENC_DEC] bit determines if the encoder or decoder function is to be tested. The result of the ECC test is provided in the OTP_ECC_DATAOUT* registers. The test steps and expected results from each test are shown below.

Automatic Decoding steps:

1. Set ECC Test to automatic OTP_ECC_TEST[MANUAL_AUTO] = 0
2. Set decoder setting OTP_ECC_TEST[ENC_DEC] = 0
3. Set decoder to single or double encoding setting with OTP_ECC_TEST[DED_SEC] (1 for DED or 0 for SEC)
4. Clear all SEC/DED faults by FAULT_RST2[RST_OTP_DATA] = 1
5. Enable ECC test OTP_ECC_TEST[ENABLE] = 1
6. Read FAULT_OTP[SEC_DET] flag for SEC or FAULT_OTP[DED_DET] flag for DED
7. Block read OTP_ECC_DATAOUT1 to OTP_ECC_DATAOUT8 to verify the decoder test results as in Table 8-30
8. Disable ECC test OTP_ECC_TEST[ENABLE] = 0

Automatic Encoding steps:

1. Set ECC TEST to automatic OTP_ECC_TEST[MANUAL_AUTO] = 0
2. Set the encoder setting using OTP_ECC_TEST[ENC_DEC] = 1
3. Enable the ECC test with OTP_ECC_TEST[ENABLE] = 1
4. Block read OTP_ECC_DATAOUT1 to OTP_ECC_DATAOUT9 to verify the encoder test results as in Table 8-30
5. Disable ECC test OTP_ECC_TEST[ENABLE] = 0