The device implemented an OVUV BIST (Built-In-Self-Test) function to test the primary OVUV protector path. Host can start the BIST run by setting [OVUV_MODE1:0] = 0b10 and [OVUV_GO] = 1. The BIST run covers:

1. OV and UV comparators thresholds:
   1. A higher and lower than the set threshold are checked to ensure the comparator is triggered correctly.
   2. If failure is detected, the corresponding FAULT_PROT2[OVCOMP_FAIL] or [UVCOMP_FAIL] bit will be set.
2. The path from the OVUV MUX to UV fault status bit and NFAULT pin:
   1. For each VS channel, a switch is open so that input to the OVUV MUX is open and will lead to a UV detection to the channel under test
   2. The BIST engine then checks the logic to assert corresponding FAULT_UV register bit and the NFAULT is set properly.
   3. The BIST engine resets the corresponding FAULT_UV bit and deasserts the NFAULT, then switches to test the next channel and repeats the process until all active channels are tested.
   4. If failure is detected, the corresponding [VPATH_FAIL] bit is set.
3. OV fault bit and NFAULT path
   1. The BIST engine forces 1 to the FAULT_OV* register, one bit at time, to ensure each FAULT_OV* register bit can be set and the NFAULT can be asserted, accordingly.
   2. If failure is detected, the corresponding [VPATH_FAIL] bit will be set.

If NFAULT is enabled, host observes NFAULT toggling during the BIST run. Upon completion of the BIST run, the OVUV comparators will be turned off. Host starts the regular OVUV mode by sending [OVUV_GO] = 1 with [OVUV_MODE1:0] = 0b11 (single channel run mode).