ZHCSTD7A December 2021 – November 2023 BQ79631-Q1
PRODUCTION DATA
The device provides a communication debug mode to ease the initial development phase. To enter this debug mode, host writes an unlock code 0xA5 to register DEBUG_CTRL_UNLOCK. Once the debug mode is unlocked, the settings in DEBUG_COMM_CTRL1 and DEBUG_COMM_CTRL2 become effective.
To exit the debug mode simply write any value but 0xA5 (for example, writing 0x00) to the DEBUG_CTRL_UNLOCK. The COMH, COML, and UART will return to their normal operation status regardless of the settings in the DEBUG_COMM_CTRL1 and DEBUG_COMM_CTRL2 registers.
Once the communication debug mode is entered, the host gains control of the following:
Control Function | Enable Bit | Description |
---|---|---|
Full COMH/L transmitter and receiver control | [USER_DAISY_EN] | If [USER_DAISY_EN] = 1, device will enable or disable its COMH/L transmitter and receiver based on the DEBUG_COMM_CTRL2 register setting. If [USER_DAISY_EN] = 0, COMH/L will be in its normal operation status even under communication debug mode. |
Mirror out the data in daisy-chain onto UART | [USER_UART_EN] | If [USER_UART_EN] = 1, host can set [UART_MIRROR_EN] = 1 to instruct the device
to translate the daisy-chain onto the UART, allowing host to read
the data being received or forwarded in the daisy-chain from the
UART interface. Data will be presented in UART communication frame
format. For stack devices, the UART TX is disabled by default. To use this feature, host also sets [UART_TX_EN] = 1. If [USER_UART_EN] = 0, any UART related debug functions are disabled. The UART will be in its normal operation status regardless of the [UART_MIRROR_EN] and [UART_TX_EN] settings. |
Slow down UART baud rate to 250 kbps | [USER_UART_EN] | If [USER_UART_EN] = 1, host can set [UART_BAUD] = 1 to change the UART baud
rate to 250 kbps. This will result in slow throughput rate on the
daisy-chain. If [USER_UART_EN] = 0, UART baud rate will stay on 1 Mbps regardless of the [UART_BAUD] setting. |
The DEBUG_COMM_STAT register has status bits indicating if UART and COMH/L are under user or hardware (device) control. The register also indicates the status of the COMH/L transmitter and receiver. This debug status register is updated per device status and is readable with or without the communication debug mode enabled.
In fact, the read-only debug registers are all readable in ACTIVE mode without communication debug mode enabled. Most of them are lower level communication fault status registers to provide extra information in a communication failure event like the DEBUG_UART*, DEBUG_COMH*, and DEBUG_COML* registers. See Section 8.3.5.2 and Section 8.5.4 for more details.