ZHCSTD7A December   2021  – November 2023 BQ79631-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 说明（续）
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Measurement System
        1. 8.3.1.1 Voltage Measurement System
          1. 8.3.1.1.1 Main ADC
            1. 8.3.1.1.1.1 VS Voltage Measurements
              1. 8.3.1.1.1.1.1 Analog Front End
              2. 8.3.1.1.1.1.2 VS Channel Measurements
              3. 8.3.1.1.1.1.3 Post-ADC Digital LPF
              4. 8.3.1.1.1.1.4 SRP and SRN Measurements
            2. 8.3.1.1.1.2 Temperature Measurements
              1. 8.3.1.1.1.2.1 DieTemp1 Measurement
              2. 8.3.1.1.1.2.2 GPIOs and TSREF Measurements
            3. 8.3.1.1.1.3 Main ADC Operation Control
              1. 8.3.1.1.1.3.1 Operation Modes and Status
          2. 8.3.1.1.2 AUX ADC
            1. 8.3.1.1.2.1 AUX Voltage Measurements
              1. 8.3.1.1.2.1.1 AUX Analog Front End
              2. 8.3.1.1.2.1.2 AUX Channel Measurements
            2. 8.3.1.1.2.2 AUX Temperature Measurements
              1. 8.3.1.1.2.2.1 DieTemp2 Measurement
              2. 8.3.1.1.2.2.2 AUX GPIO Measurements
            3. 8.3.1.1.2.3 MISC Measurements
            4. 8.3.1.1.2.4 AUX ADC Operation Control
          3. 8.3.1.1.3 Synchronization Between MAIN and AUX ADC Measurements
        2. 8.3.1.2 Current Sense ADC
      2. 8.3.2 OVUV Detection
        1. 8.3.2.1 OVUV Operation Modes
        2. 8.3.2.2 OVUV Control and Status
          1. 8.3.2.2.1 OVUV Control
          2. 8.3.2.2.2 OVUV Status
      3. 8.3.3 Power Supplies
        1. 8.3.3.1 AVAO_REF and AVDD_REF
        2. 8.3.3.2 LDOIN
        3. 8.3.3.3 AVDD
        4. 8.3.3.4 DVDD
        5. 8.3.3.5 CVDD and NEG5V
        6. 8.3.3.6 TSREF
      4. 8.3.4 GPIO Configuration
      5. 8.3.5 Communication, OTP, Diagnostic Control
        1. 8.3.5.1 Communication
          1. 8.3.5.1.1 Serial Interface
            1. 8.3.5.1.1.1 UART Physical Layer
              1. 8.3.5.1.1.1.1 UART Transmitter
              2. 8.3.5.1.1.1.2 UART Receiver
              3. 8.3.5.1.1.1.3 COMM CLEAR
            2. 8.3.5.1.1.2 Command and Response Protocol
              1. 8.3.5.1.1.2.1 Transaction Frame Structure
                1. 8.3.5.1.1.2.1.1 Frame Initialization Byte
                2. 8.3.5.1.1.2.1.2 Device Address Byte
                3. 8.3.5.1.1.2.1.3 Register Address Bytes
                4. 8.3.5.1.1.2.1.4 Data Bytes
                5. 8.3.5.1.1.2.1.5 CRC Bytes
                6. 8.3.5.1.1.2.1.6 Calculating Frame CRC Value
                7. 8.3.5.1.1.2.1.7 Verifying Frame CRC
              2. 8.3.5.1.1.2.2 Transaction Frame Examples
                1. 8.3.5.1.1.2.2.1 Single Device Read/Write
                2. 8.3.5.1.1.2.2.2 Stack Read/Write
                3. 8.3.5.1.1.2.2.3 Broadcast Read/Write
                4. 8.3.5.1.1.2.2.4 Broadcast Write Reverse Direction
          2. 8.3.5.1.2 Daisy-Chain Interface
            1. 8.3.5.1.2.1 Daisy-Chain Transmitter and Receiver Functionality
            2. 8.3.5.1.2.2 Daisy-Chain Protocol
          3. 8.3.5.1.3 Start Communication
            1. 8.3.5.1.3.1 Identify Base and Stack
            2. 8.3.5.1.3.2 Auto-Addressing
              1. 8.3.5.1.3.2.1 Setting Up the Device Addresses
              2. 8.3.5.1.3.2.2 Setting Up COMM_CTRL[STACK_DEV] and [TOP_STACK]
              3. 8.3.5.1.3.2.3 Storing Device Address to OTP
            3. 8.3.5.1.3.3 Synchronize Daisy-Chain DLL
            4. 8.3.5.1.3.4 Ring Communication
          4. 8.3.5.1.4 Communication Timeout
            1. 8.3.5.1.4.1 Short Communication Timeout
            2. 8.3.5.1.4.2 Long Communication Timeout
          5. 8.3.5.1.5 Communication Debug Mode
          6. 8.3.5.1.6 Multidrop Configuration
          7. 8.3.5.1.7 SPI Master
          8. 8.3.5.1.8 SPI Loopback
        2. 8.3.5.2 Fault Handling
          1. 8.3.5.2.1 Fault Status Hierarchy
            1. 8.3.5.2.1.1 Debug Registers
          2. 8.3.5.2.2 Fault Masking and Reset
            1. 8.3.5.2.2.1 Fault Masking
            2. 8.3.5.2.2.2 Fault Reset
          3. 8.3.5.2.3 Fault Signaling
            1. 8.3.5.2.3.1 Fault Status Transmitting in ACTIVE Mode
            2. 8.3.5.2.3.2 Fault Status Transmitting in SLEEP Mode
            3. 8.3.5.2.3.3 Heartbeat and Fault Tone
        3. 8.3.5.3 Nonvolatile Memory
          1. 8.3.5.3.1 OTP Page Status
          2. 8.3.5.3.2 OTP Programming
        4. 8.3.5.4 Diagnostic Control/Status
          1. 8.3.5.4.1 Power Supplies Check
            1. 8.3.5.4.1.1 Power Supply Diagnostic Check
            2. 8.3.5.4.1.2 Power Supply BIST
          2. 8.3.5.4.2 Thermal Shutdown and Warning Check
            1. 8.3.5.4.2.1 Thermal Shutdown
            2. 8.3.5.4.2.2 Thermal Warning
          3. 8.3.5.4.3 Oscillators Watchdog
          4. 8.3.5.4.4 OTP Error Check
            1. 8.3.5.4.4.1 OTP CRC Test and Faults
            2. 8.3.5.4.4.2 OTP Margin Read
            3. 8.3.5.4.4.3 Error Check and Correct (ECC) OTP
          5. 8.3.5.4.5 OVUV Detection Check
            1. 8.3.5.4.5.1 Parity Check
            2. 8.3.5.4.5.2 OVUV DAC Check
            3. 8.3.5.4.5.3 OVUV Protector BIST
          6. 8.3.5.4.6 Diagnostic Through ADC Comparison
            1. 8.3.5.4.6.1 VS Voltage Measurement Check
            2. 8.3.5.4.6.2 Temperature Measurement Check
            3. 8.3.5.4.6.3 VS and AUX Open Wire Check
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 SHUTDOWN Mode
          1. 8.4.1.1.1 Exit SHUTDOWN Mode
          2. 8.4.1.1.2 Enter SHUTDOWN Mode
        2. 8.4.1.2 SLEEP Mode
          1. 8.4.1.2.1 Exit SLEEP Mode
          2. 8.4.1.2.2 Enter SLEEP Mode
        3. 8.4.1.3 ACTIVE Mode
          1. 8.4.1.3.1 Exit ACTIVE Mode
          2. 8.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode
          3. 8.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode
      2. 8.4.2 Device Reset
      3. 8.4.3 Ping and Tone
        1. 8.4.3.1 Ping
        2. 8.4.3.2 Tone
        3. 8.4.3.3 Ping and Tone Propagation
    5. 8.5 Register Maps
      1. 8.5.1 OTP Shadow Register Summary
      2. 8.5.2 Read/Write Register Summary
      3. 8.5.3 Read-Only Register Summary
      4. 8.5.4 Register Field Descriptions
        1. 8.5.4.1  Device Addressing Setup
          1. 8.5.4.1.1 DIR0_ADDR_OTP
          2. 8.5.4.1.2 DIR1_ADDR_OTP
          3. 8.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 8.5.4.1.4 DIR0_ADDR
          5. 8.5.4.1.5 DIR1_ADDR
        2. 8.5.4.2  Device ID and Scratch Pad
          1. 8.5.4.2.1 PARTID
          2. 8.5.4.2.2 DEV_REVID
          3. 8.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 8.5.4.3  General Configuration and Control
          1. 8.5.4.3.1  DEV_CONF
          2. 8.5.4.3.2  PWR_TRANSIT_CONF
          3. 8.5.4.3.3  COMM_TIMEOUT_CONF
          4. 8.5.4.3.4  TX_HOLD_OFF
          5. 8.5.4.3.5  STACK_RESPONSE
          6. 8.5.4.3.6  COMM_CTRL
          7. 8.5.4.3.7  CONTROL1
          8. 8.5.4.3.8  CONTROL2
          9. 8.5.4.3.9  CUST_CRC_HI
          10. 8.5.4.3.10 CUST_CRC_LO
          11. 8.5.4.3.11 CUST_CRC_RSLT_HI
          12. 8.5.4.3.12 CUST_CRC_RSLT_LO
        4. 8.5.4.4  Operation Status
          1. 8.5.4.4.1 DIAG_STAT
          2. 8.5.4.4.2 ADC_STAT1
          3. 8.5.4.4.3 ADC_STAT2
          4. 8.5.4.4.4 GPIO_STAT
          5. 8.5.4.4.5 DEV_STAT
        5. 8.5.4.5  ADC Configuration and Control
          1. 8.5.4.5.1  ADC_CONF1
          2. 8.5.4.5.2  ADC_CONF2
          3. 8.5.4.5.3  MAIN_ADC_CAL1
          4. 8.5.4.5.4  MAIN_ADC_CAL2
          5. 8.5.4.5.5  AUX_ADC_CAL1
          6. 8.5.4.5.6  AUX_ADC_CAL2
          7. 8.5.4.5.7  CS_ADC_CAL1
          8. 8.5.4.5.8  CS_ADC_CAL2
          9. 8.5.4.5.9  ADC_CTRL1
          10. 8.5.4.5.10 ADC_CTRL2
          11. 8.5.4.5.11 ADC_CTRL3
        6. 8.5.4.6  ADC Measurement Results
          1. 8.5.4.6.1  VS16_HI/LO
          2. 8.5.4.6.2  VS15_HI/LO
          3. 8.5.4.6.3  VS14_HI/LO
          4. 8.5.4.6.4  VS13_HI/LO
          5. 8.5.4.6.5  VS12_HI/LO
          6. 8.5.4.6.6  VS11_HI/LO
          7. 8.5.4.6.7  VS10_HI/LO
          8. 8.5.4.6.8  VS9_HI/LO
          9. 8.5.4.6.9  VS8_HI/LO
          10. 8.5.4.6.10 VS7_HI/LO
          11. 8.5.4.6.11 VS6_HI/LO
          12. 8.5.4.6.12 VS5_HI/LO
          13. 8.5.4.6.13 VS4_HI/LO
          14. 8.5.4.6.14 VS3_HI/LO
          15. 8.5.4.6.15 VS2_HI/LO
          16. 8.5.4.6.16 VS1_HI/LO
          17. 8.5.4.6.17 CSAUX_HI/LO
          18. 8.5.4.6.18 TSREF_HI/LO
          19. 8.5.4.6.19 GPIO1_HI/LO
          20. 8.5.4.6.20 GPIO2_HI/LO
          21. 8.5.4.6.21 GPIO3_HI/LO
          22. 8.5.4.6.22 GPIO4_HI/LO
          23. 8.5.4.6.23 GPIO5_HI/LO
          24. 8.5.4.6.24 GPIO6_HI/LO
          25. 8.5.4.6.25 GPIO7_HI/LO
          26. 8.5.4.6.26 GPIO8_HI/LO
          27. 8.5.4.6.27 DIETEMP1_HI/LO
          28. 8.5.4.6.28 DIETEMP2_HI/LO
          29. 8.5.4.6.29 AUX_IN_HI/LO
          30. 8.5.4.6.30 AUX_GPIO_HI/LO
          31. 8.5.4.6.31 AUX_PWR_HI/LO
          32. 8.5.4.6.32 AUX_REFL_HI/LO
          33. 8.5.4.6.33 AUX_VBG2_HI/LO
          34. 8.5.4.6.34 AUX_AVAO_REF_HI/LO
          35. 8.5.4.6.35 AUX_AVDD_REF_HI/LO
          36. 8.5.4.6.36 AUX_OV_DAC_HI/LO
          37. 8.5.4.6.37 AUX_UV_DAC_HI/LO
          38. 8.5.4.6.38 AUX_VCM1_HI/LO
          39. 8.5.4.6.39 REFH_HI/LO
          40. 8.5.4.6.40 DIAG_MAIN_HI/LO
          41. 8.5.4.6.41 DIAG_AUX_HI/LO
          42. 8.5.4.6.42 CURRENT_HI/MID/LO
        7. 8.5.4.7  Protector Configuration and Control
          1. 8.5.4.7.1 OV_THRESH
          2. 8.5.4.7.2 UV_THRESH
          3. 8.5.4.7.3 UV_DISABLE1
          4. 8.5.4.7.4 UV_DISABLE2
          5. 8.5.4.7.5 OVUV_CTRL
        8. 8.5.4.8  GPIO Configuration
          1. 8.5.4.8.1 GPIO_CONF1
          2. 8.5.4.8.2 GPIO_CONF2
          3. 8.5.4.8.3 GPIO_CONF3
          4. 8.5.4.8.4 GPIO_CONF4
        9. 8.5.4.9  SPI Master
          1. 8.5.4.9.1 SPI_CONF
          2. 8.5.4.9.2 SPI_EXE
          3. 8.5.4.9.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 8.5.4.9.4 SPI_RX3, SPI_RX2, and SPI_RX1
        10. 8.5.4.10 Diagnostic Control
          1. 8.5.4.10.1 DIAG_OTP_CTRL
          2. 8.5.4.10.2 DIAG_COMM_CTRL
          3. 8.5.4.10.3 DIAG_PWR_CTRL
          4. 8.5.4.10.4 DIAG_COMP_CTRL1
          5. 8.5.4.10.5 DIAG_COMP_CTRL2
          6. 8.5.4.10.6 DIAG_COMP_CTRL3
          7. 8.5.4.10.7 DIAG_COMP_CTRL4
          8. 8.5.4.10.8 DIAG_PROT_CTRL
        11. 8.5.4.11 Fault Configuration and Reset
          1. 8.5.4.11.1 FAULT_MSK1
          2. 8.5.4.11.2 FAULT_MSK2
          3. 8.5.4.11.3 FAULT_RST1
          4. 8.5.4.11.4 FAULT_RST2
        12. 8.5.4.12 Fault Status
          1. 8.5.4.12.1  FAULT_SUMMARY
          2. 8.5.4.12.2  FAULT_COMM1
          3. 8.5.4.12.3  FAULT_COMM2
          4. 8.5.4.12.4  FAULT_COMM3
          5. 8.5.4.12.5  FAULT_OTP
          6. 8.5.4.12.6  FAULT_SYS
          7. 8.5.4.12.7  FAULT_PROT1
          8. 8.5.4.12.8  FAULT_PROT2
          9. 8.5.4.12.9  FAULT_OV1
          10. 8.5.4.12.10 FAULT_OV2
          11. 8.5.4.12.11 FAULT_UV1
          12. 8.5.4.12.12 FAULT_UV2
          13. 8.5.4.12.13 FAULT_COMP_GPIO
          14. 8.5.4.12.14 FAULT_COMP_VSAUX1
          15. 8.5.4.12.15 FAULT_COMP_VSAUX2
          16. 8.5.4.12.16 FAULT_COMP_VSOW1
          17. 8.5.4.12.17 FAULT_COMP_VSOW2
          18. 8.5.4.12.18 FAULT_COMP_AUXOW1
          19. 8.5.4.12.19 FAULT_COMP_AUXOW2
          20. 8.5.4.12.20 FAULT_COMP_MISC
          21. 8.5.4.12.21 FAULT_PWR1
          22. 8.5.4.12.22 FAULT_PWR2
          23. 8.5.4.12.23 FAULT_PWR3
        13. 8.5.4.13 Debug Control and Status
          1. 8.5.4.13.1  DEBUG_CTRL_UNLOCK
          2. 8.5.4.13.2  DEBUG_COMM_CTRL1
          3. 8.5.4.13.3  DEBUG_COMM_CTRL2
          4. 8.5.4.13.4  DEBUG_COMM_STAT
          5. 8.5.4.13.5  DEBUG_UART_RC
          6. 8.5.4.13.6  DEBUG_UART_RR_TR
          7. 8.5.4.13.7  DEBUG_COMH_BIT
          8. 8.5.4.13.8  DEBUG_COMH_RC
          9. 8.5.4.13.9  DEBUG_COMH_RR_TR
          10. 8.5.4.13.10 DEBUG_COML_BIT
          11. 8.5.4.13.11 DEBUG_COML_RC
          12. 8.5.4.13.12 DEBUG_COML_RR_TR
          13. 8.5.4.13.13 DEBUG_UART_DISCARD
          14. 8.5.4.13.14 DEBUG_COMH_DISCARD
          15. 8.5.4.13.15 DEBUG_COML_DISCARD
          16. 8.5.4.13.16 DEBUG_UART_VALID_HI/LO
          17. 8.5.4.13.17 DEBUG_COMH_VALID_HI/LO
          18. 8.5.4.13.18 DEBUG_COML_VALID_HI/LO
          19. 8.5.4.13.19 DEBUG_OTP_SEC_BLK
          20. 8.5.4.13.20 DEBUG_OTP_DED_BLK
        14. 8.5.4.14 OTP Programming Control and Status
          1. 8.5.4.14.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 8.5.4.14.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 8.5.4.14.3 OTP_PROG_CTRL
          4. 8.5.4.14.4 OTP_ECC_TEST
          5. 8.5.4.14.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 8.5.4.14.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 8.5.4.14.7 OTP_PROG_STAT
          8. 8.5.4.14.8 OTP_CUST1_STAT
          9. 8.5.4.14.9 OTP_CUST2_STAT
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Base Device Application Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  PACK+ and FUSE Measurement
          2. 9.2.1.2.2  Insulation Measurement
          3. 9.2.1.2.3  LINK+/- Measurement
          4. 9.2.1.2.4  CHARGE+/– Measurement
          5. 9.2.1.2.5  Overcurrent Detection Scheme Using OVUV Comparators
          6. 9.2.1.2.6  Unused Pins
          7. 9.2.1.2.7  Current Sense Input
          8. 9.2.1.2.8  VPWR and External NPN
          9. 9.2.1.2.9  Power Supplies, Reference Input
          10. 9.2.1.2.10 GPIO For Thermistor Inputs
          11. 9.2.1.2.11 UART, NFAULT
          12. 9.2.1.2.12 Daisy-Chain Isolation
            1. 9.2.1.2.12.1 Devices Connected on the Same PCB
            2. 9.2.1.2.12.2 Devices Connected on Different PCBs
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Daisy Device Application Circuit
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 11.1.3 Voltage Sensing
      4. 11.1.4 Daisy-Chain Communication
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

over operating -40℃ to 125℃ free-air temperature range, VVPWR = 9V to 15V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
TSHUT Thermal shutdown (rising direction) 130 137 152 °C
TSHUT_FALL Thermal shutdown (falling direction) 112 129 °C
TSHUT_HYS Thermal shutdown (rising - falling direction) 20 °C
TWARN_RANGE Thermal warning Threshold (rising direction) 85 115 °C
TWARN_HYS Thermal warning hysteresis (falling direction) 10 °C
TWARN_ACC Thermal warning accuracy (+/-) 5 °C
SUPPLY CURRENTS
ISHDN Supply current in SHUTDOWN mode Sum of both IVPWR and ILDOIN 16 23 µA
ISLP(IDLE) Baseline supply current in SLEEP mode. No fault, no protector comparator Sum of both IVPWR and ILDOIN
TA = -20℃ to 65℃		 120 160 µA
Sum of both IVPWR and ILDOIN
TA = -40℃ to 125℃		 220 µA
IACT(IDLE) Baseline supply current in ACTIVE mode Sum of both IVPWR and ILDOIN
No fault, no communication, no protector comparator		 10.4 11.6 mA
IPROTCOMP Additional supply current when protector comparator is on Either OV/UV protector is enabled. Other functions are inactive 20 60 µA
IADC Additional supply current when CS/
main and aux ADC are enabled		 Both CS/Main ADC are on, in continiously mode, Other functions are inactive 1.8 2.4 mA
IADC Additional supply current when ADC is enabled Main or Aux ADC on, and conversion is in progress. Other functions are inactive  0.4 0.6 mA
2 ADCs on, and conversion is in progress. Other functions are inactive  (not applicable if current sense ADC is availbe in this device) 0.6 0.9 mA
IVPWR Supply current goes into VPWR pin ACTIVE Mode 150 µA
SLEEP Mode 25 µA
SHUTDOWN Mode 5 µA
ICOMT Additional supply current during daisy-chain broadcast read of 128-byte data Use transformer isolation for daisy-chain interface 10 mA
ICOMC Additional supply current during daisy-chain broadcast read of 128-byte data Use capacitor or capacitor and choke isolation for daisy-chain interface 10 mA
IOW_SINK Sink current for open wire test, applies to VS1 to VS16 and AUX1 to AUX 4 380 500 600 µA
IOW_SOURCE Source current for open wire test, applies to VS0 and AUX0 380 500 600 µA
ILEAK_CS Leakage current SRP and SRN pin Main and CS ADC is off 0.2 µA
ILEAK Leakage current on VS, AUX pins VS, AUX pins with ADC off.
 		 0.1 µA
VSR_OW Clamped voltage when IOW_SORUCE is enabled for SRP and SRN 0.9 V
Supplies (LDOIN)
VLDOIN LDOIN voltage No OTP programming 5.9 6 6.1 V
 OTP programming 7.9 8 8.1 V
Supplies (CVDD)
VCVDD CVDD output voltage ACTIVE and SLEEP mode 4.9 5 5.1 V
SHUTDOWN mode, no external Iload 3.95 6 V
SHUTDOWN mode, max external Iload = 5mA 3.4 5.5 V
VCVDD_LDRG CVDD load regulation ACTIVE/SLEEP mode, max external Iload = 10mA –30 30 mV
VCVDD_OV CVDD OV threshold ACTIVE/SLEEP mode, max external Iload = 10mA 5.3 5.5 5.7 V
VCVDD_OVHYS CVDD OV Hystersis ACTIVE/SLEEP mode, max external Iload = 10mA 130 150 170 mV
VCVDD_UV CVDD UV threshold SHUTDOWN mode 3.5 V
ACTIVE/SLEEP mode, max external Iload = 10mA 4.3 4.45 4.65 V
VCVDD_UVHYS CVDD UV Hystersis 260 mV
VCVDD_ILIMIT CVDD current limit ACTIVE, SLEEP 35 60 85 mA
Supplies (AVDD)
VAVDD AVDD output voltage CSUPPLIES = 1µF, ACTIVE mode 4.85 5 5.21 V
VAVDD_OV AVDD OV threshold CSUPPLIES = 1µF, ACTIVE mode 5.25 5.5 5.7 V
VAVDD_OVHYS AVDD OV Hystersis CSUPPLIES = 1µF, ACTIVE mode 135 155 165 mV
VAVDD_UV AVDD UV threshold CSUPPLIES = 1µF, ACTIVE mode 4.25 4.45 4.6 V
VAVDD_UVHYS AVDD UV Hystersis CSUPPLIES = 1µF, ACTIVE mode 235 340 430 mV
VAVDD_ILIMIT AVDD current limit CSUPPLIES = 1µF 10 30 50 mA
Supplies (DVDD)
VDVDD DVDD output voltage CSUPPLIES = 1µF, ACTIVE mode 1.65 1.8 1.95 V
VDVDD_OV DVDD OV threshold  CSUPPLIES = 1µF, ACTIVE mode 1.95 2.1 2.3 V
VDVDD_OVHYS DVDD OV Hystersis CSUPPLIES = 1µF, ACTIVE mode 40 65 120 mV
VDVDD_UV DVDD UV threshold  CSUPPLIES = 1µF, ACTIVE mode 1.623 1.65 1.71 V
VDVDD_UVHYS DVDD UV Hystersis CSUPPLIES = 1µF, ACTIVE mode 15 50 73 mV
VDVDD_ILIMIT DVDD current limit 13 30 53 mA
Supplies (TSREF)
VTSREF TSREF output voltage CSUPPLIES = 1µF, ACTIVE mode 4.975 5 5.025 V
VTSREF_LDRG TSREF load regulation Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode –30 30 mV
VTSREF_OV TSREF OV threshold Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 5.2 5.6 5.8 V
VTSREF_OVHYS TSREF OV Hystersis Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 98 110 120 mV
VTSREF_UV TSREF UV threshold Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 4.0 4.2 4.4 V
VTSREF_UVHYS TSREF UV Hystersis Iload = 4mA, CSUPPLIES = 1µF, ACTIVE mode 300 350 400 mV
VTSREF_ILIMIT TSREF current limit Device in ACTIVE Mode 15 30 52 mA
Negative Charge Pump (NEG5V)
VNEG5V NEG5V pin voltage CNEG5V = 0.1µF -5.3 -4.6 -4.0 V
VNEG5V_UV NEG5V UV threshold (rising) CNEG5V = 0.1µF -4.1 -3.5 -3.0 V
VNEG5V_UVRECOV NEG5V UV Recovery CNEG5V = 0.1µF -4.3 -3.8 -3.3 V
ADC Resolution
ENOBMAIN Main ADC Effective number of
bits		     16   bits
ENOBAUX AUX ADC Effective number of bits     14   bits
VLSB_ADC Main and AUX ADC Resolution for input voltage measurement   190.73   µV/LSB
VLSB_CSADC_AUX AUX CSADC Resolution for (SRP-SRN) measurement 30.52 µV/LSB
VLSB_MAIN_DIETEMP1 DieTemp1 resolution (Main ADC) ADC measurement is centered with 0x000 = 0oC   0.025   °C/LSB
VLSB_AUX_DIETEMP2 DieTemp2 resolution (AUX ADC) ADC measurement is centered with 0x000 = 0oC   0.025   °C/LSB
VLSB_AUX_VPWR VPWR resolution (AUX ADC) Applies to VPWR voltage measurement from AUX ADC   3.05   mV/LSB
VLSB_GPIO GPIO resolution (Main & AUX
ADC)		   152.59   µV/LSB
VLSB_TSREF TSREF resolution (Main ADC) 169.54 µV/LSB
VLSB_DIAG Diagnostic measurements resolution
 		 REFL, VBG2, LPBG5, VCM, AVAO_REF, AVDD_REF, all the HW protector DAC
 		   152.59   µV/LSB
VLSB_CS Current Sense ADC resolution (24-bit result) Reading CURRENT_HI/MID/LO registers 14.9 nV/LSB
ADC Accuracy
IVS_DELTA VSn to VSn-1 input current delta (when Main ADC is on) TA = -20oC to 65oC     1.8 µA
TA = -40oC to 105oC     2 µA
IVS VSn input current (when Main ADC is on)     12 µA
RAUX_INPUT AUX pin input impedance (when AUX ADC is on) 16 MΩ
VACC_MAIN Total channel accuracy for main ADC VS measurement, LPF_VS[2:0] = 0x03 setting; 2V<VIN<4.5V; TA=25oC -2.2 1.5 mV
2V<VIN<4.5V; -20oC<TA<65oC -3.0 2.4 mV
2V<VIN<4.5V; -40oC<TA<105oC -3.5 2.6 mV
2V<VIN<4.5V; -40oC<TA<125oC -3.5 2.6 mV
1V<VIN< 5V; -40oC<TA<125oC -3.7 2.8 mV
-2V<VIN< 5V; -40oC<TA<125oC -4.5 3.2 mV
VACC_AUX Total channel accuracy for AUX ADC measurement (excluding VPWR and GPIO accuracy); 2V<VIN<4.5V; TA=25oC -7.5 5.4 mV
2V<VIN<4.5V; -20oC<TA<65oC -8.0 6.3 mV
2V<VIN<4.5V; -40oC<TA<105oC -9.0 6.3 mV
2V<VIN<4.5V; -40oC<TA<125oC -9.0 6.5 mV
1V<VIN< 5V; -40oC<TA<125oC -9.0 6.6 mV
0V<VIN< 5V; -40oC<TA<125oC -9.0 6.6 mV
V(MAIN-AUX) Main - AUX measurement during VIN diagnostic. Same input voltage to both ADC under same TA; 2V<VIN<4.5V; TA=25oC -7.1   6.1 mV
2V<VIN<4.5V; -20oC<TA<65oC -7.8   6.6 mV
2V<VIN<4.5V; -40oC<TA<105oC -7.8   6.6 mV
2V<VIN<4.5V; -40oC<TA<125oC -7.8 6.7 mV
1V<VIN< 5V; -40oC<TA<125oC -7.9 6.9 mV
0V<VIN< 5V; -40oC<TA<125oC -7.9   6.9 mV
VACC_MAIN_GPIO_RATIO Measured GPIO from Main ADC/measured TSREF from Main ADC; 0.08V<VIN<0.2V, 85oC<TA<125oC -0.20 0.20 %
0.2V<VIN<4.6V, -40oC<TA<105oC -0.20 0.20 %
4.6V<VIN<4.8V, -40oC<TA<-20oC -0.30 0.30 %
VACC_AUX_GPIO_RATIO Measured GPIO from AUX ADC/measured TSREF from AUX ADC; 0.08V<VIN<0.2V, 85oC<TA<125oC -0.20 0.20 %
0.2V<VIN<4.6V, -40oC<TA<105oC -0.20 0.20 %
4.6V<VIN<4.8V, -40oC<TA<-20oC -0.30 0.30 %
VACC_MAIN_GPIO_ABS Total channel accuracy for GPIO measurement (Main ADC); 0.08V<VIN<0.2V, 85oC<TA<125oC -4.00 4.00 mV
0.2V<VIN<4.6V, -40oC<TA<105oC -5.00 3.00 mV
4.6V<VIN<4.8V, -40oC<TA<-20oC -4.00 4.00 mV
VACC_AUX_GPIO_ABS Accuracy from AUX ADC on GPIO 0.08V<VIN<0.2V, 85oC<TA<125oC -6.00 6.00 mV
0.2V<VIN<4.6V, -40oC<TA<105oC -6.00 6.00 mV
4.6V<VIN<4.8V, -40oC<TA<-20oC -6.00 6.00 mV
VACC_MAIN_CS Total channel accuracy for (SRP-SRN) from CSADC AUX measurement LPF_SR[2:0] = 0x00 -1.1 1.1 mV
VACC_AUX_REFL AUX ADC measurement result 1.092 1.1 1.106 V
VACC_AUX_VBG2 AUX ADC measurement result 1.092 1.1 1.106 V
VACC_AUX_VCM AUX ADC measurement result 2.400 2.5 2.550 V
VACC_AUX_AVAO_REF AUX ADC measurement result 2.400 2.47 2.550 V
VACC_AUX_AVDD_REF AUX ADC measurement result 2.400 2.47 2.550 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 4.475V; TA = -20oC to 65oC 4.450 4.500 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 4.475V; TA = -40oC to 105oC 4.445 4.500 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 4.475V; TA = -40oC to 125oC 4.445 4.500 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 3.8V 3.770 3.825 V
VACC_AUX_OVDAC AUX ADC measurement result Setting at 3V 2.970 3.030 V
VACC_AUX_UVDAC AUX ADC measurement result Setting at 3.1V 3.095 3.1 3.150 V
VACC_MAIN_TSREF Main ADC measurement result 4.975 5 5.025 V
VACC_MAIN_DIETEMP Total channel accuracy for Die Temp1 measurement (+/-) 3 ℃
VACC_AUX_DIETEMP Total channel accuracy for Die Temp2 measurement (+/-) 6 ℃
ISRP_N_Diff Differential SRN/SRP input current (CS and main ADC are on) Apply 100mV differential acrsoss SRP/SRN   1.4 µA
VRANGE_CS Effective input range of CS ADC -100 100 mV
VNOISE_CS
CS ADC input referred noise
 		 CS_DS[1:0] = 11, CS ADC in continious mode, short SRP/SRN at pins 0.71 uVRMS
Gain_error_cs_room_uncal Gain error of CS ADC @25oC, it could be single temp piont calibrated out TA = 25oC, CS_DS[1:0] = 01, measured at -75mV and 75mV -0.6 0.6 %
Gain_error_cs_drift1 Gain error of CS ADC drift over temperature, |VRANGE_CS | <100mV TA = -20oC to 85oC, CS_DS[1:0] = 01, measured at 50mV and 75mV   0.3 %
TA = -40oC to 105oC, CS_DS[1:0] = 01, measured at 50mV and 75mV   0.3 %
Offset_cs_room_uncal Input referred offset error of CS ADC @ 25oC, it could be single temp piont calibrated out TA = 25oC, CS_DS[1:0] = 01, short SRP/SRN at pins -6 6 µV
Offset_cs_drift Input referred offset error drift over temperature TA = -40oC to -20oC, CS_DS[1:0] = 01, short SRP/SRN at pins -2.5   2.5 µV
TA = -20oC to 105oC, CS_DS[1:0] = 01, short SRP/SRN at pins -1.8 1.8 µV
Reference Voltages
VREFH REFHP to REFHM voltage 4.975 5 5.025 V
HW Voltage Comparator/Protector (OV/UV)
VOV_COMP_RANGE OV comparator detection threshold setting range (not accuracy) Step of 25mV 2700   3000 mV
Step of 25mV 3600   3800 mV
Step of 25mV 4175   4500 mV
VOV_COMP_HYS OV comparator hysteresis after
detection		     50   mV
VOV_COMP_ACC OV comparator accuracy TA = -20oC to 65oC -24   24 mV
TA = -40oC to 105oC -28   28 mV
VUV_COMP_RANGE UV comparator detection threshold  setting range (not accuracy) Step of 50mV 1200   3100 mV
VUV_COMP_HYS UV comparator hysteresis after detection     50   mV
VUV_COMP_ACC UV comparator accuracy TA = -20oC to 65oC -35   35 mV
TA = -40oC to 105oC -50   50 mV
Digital I/Os (TX, RX, GPIO, SPI master)
VOH Output as logic level high (TX, GPIO as output) GPIO is configured as output. IOUT = 1mA VCVDD-0.3     V
VOL Output as logic level low (TX, NFAULT, GPIO as output) GPIO is configured as output. IOUT = 1mA     0.3 V
VIH Input as logic level high (RX, GPIO as fault input) GPIO is configured as input. IOUT = 1mA 0.75 x VCVDD     V
VIL Input as logic level low (RX, GPIO as fault input) GPIO is configured as input. IOUT = 1mA     0.25 x VCVDD V
RWK_PU GPIO weak pull-up resistance 20 37 60 KΩ
RWK_PD GPIO weak pull-down resistance 20 40 60 KΩ
COML and COMH
RDCTX Transmitter output impedance (COML and COMH) 18 Ω
RDCCM Common mode impedance (COML and COMH)   45   kΩ
VDCCM Common mode voltage  (COML and COMH) 2.21 2.5 2.76 V
VCOMM_DATA1 Receiver threshold range (VCOMP-VCOML) form communication CODE:0 0.4 1.2 V
VCOMM_TONE1 Receiver threshold range (VCOMP-VCOML) form Tone CODE:0 0.4 1.2 V
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