ZHCSJU4I
November 2006 – September 2018
CC1020
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
功能方框图
2
修订历史记录
3
Terminal Configuration and Functions
3.1
Pin Diagram
3.2
Pin Configuration
4
Specifications
4.1
Absolute Maximum Ratings
4.2
ESD Ratings
4.3
Recommended Operating Conditions
4.4
RF Transmit
4.5
RF Receive
4.6
RSSI / Carrier Sense
4.7
Intermediate Frequency (IF)
4.8
Crystal Oscillator
4.9
Frequency Synthesizer
4.10
Digital Inputs and Outputs
4.11
Current Consumption
4.12
Thermal Resistance Characteristics for VQFNP Package
5
Detailed Description
5.1
Overview
5.2
Functional Block Diagram
5.3
Configuration Overview
5.3.1
Configuration Software
5.4
Microcontroller Interface
5.4.1
Configuration Interface
5.4.2
Signal Interface
5.4.3
PLL Lock Signal
5.5
4-wire Serial Configuration Interface
5.6
Signal Interface
5.6.1
Synchronous NRZ Mode
5.6.2
Transparent Asynchronous UART Mode
5.6.3
Synchronous Manchester Encoded Mode
5.6.3.1
Manchester Encoding and Decoding
5.7
Data Rate Programming
5.8
Frequency Programming
5.8.1
Dithering
5.9
Receiver
5.9.1
IF Frequency
5.9.2
Receiver Channel Filter Bandwidth
5.9.3
Demodulator, Bit Synchronizer, and Data Decision
5.9.4
Receiver Sensitivity Versus Data Rate and Frequency Separation
5.9.5
RSSI
5.9.6
Image Rejection Calibration
5.9.7
Blocking and Selectivity
5.9.8
Linear IF Chain and AGC Settings
5.9.9
AGC Settling
5.9.10
Preamble Length and Sync Word
5.9.11
Carrier Sense
5.9.12
Automatic Power-up Sequencing
5.9.13
Automatic Frequency Control
5.9.14
Digital FM
5.10
Transmitter
5.10.1
FSK Modulation Formats
5.10.2
Output Power Programming
5.10.3
TX Data Latency
5.10.4
Reducing Spurious Emission and Modulation Bandwidth
5.11
Input and Output Matching and Filtering
5.12
Frequency Synthesizer
5.12.1
VCO, Charge Pump and PLL Loop Filter
5.12.2
VCO and PLL Self-Calibration
5.12.3
PLL Turn-on Time Versus Loop Filter Bandwidth
5.12.4
PLL Lock Time Versus Loop Filter Bandwidth
5.13
VCO and LNA Current Control
5.14
Power Management
5.15
On-Off Keying (OOK)
5.16
Crystal Oscillator
5.17
Built-in Test Pattern Generator
5.18
Interrupt on Pin DCLK
5.18.1
Interrupt Upon PLL Lock
5.18.2
Interrupt Upon Received Signal Carrier Sense
5.19
PA_EN and LNA_EN Digital Output Pins
5.19.1
Interfacing an External LNA or PA
5.19.2
General Purpose Output Control Pins
5.19.3
PA_EN and LNA_EN Pin Drive
5.20
System Considerations and Guidelines
5.20.1
SRD Regulations
5.20.2
Narrowband Systems
5.20.3
Low Cost Systems
5.20.4
Battery Operated Systems
5.20.5
High Reliability Systems
5.20.6
Frequency Hopping Spread Spectrum Systems (FHSS)
5.21
Antenna Considerations
5.22
Configuration Registers
5.22.1
Memory
6
Applications, Implementation, and Layout
6.1
Application Information
6.1.1
Typical Application
6.2
Design Requirements
6.2.1
Input and Output Matching
6.2.2
Bias Resistor
6.2.3
PLL Loop Filter
6.2.4
Crystal
6.2.5
Additional Filtering
6.2.6
Power Supply Decoupling and Filtering
6.3
PCB Layout Recommendations
7
器件和文档支持
7.1
器件支持
7.1.1
器件命名规则
7.2
文档支持
7.2.1
Community Resources
7.3
商标
7.4
静电放电警告
7.5
Export Control Notice
7.6
Glossary
8
机械、封装和可订购信息
8.1
封装信息
封装选项
机械数据 (封装 | 引脚)
RSS|32
MPQF200B
散热焊盘机械数据 (封装 | 引脚)
RSS|32
QFND548
订购信息
zhcsju4i_oa
1.1
特性
真正的单芯片 UHF 射频收发器
频率范围为 402MHz 至 470MHz
和 804MHz 至 930MHz
高灵敏度
针对 12.5kHz 通道高达 –118dBm
可编程输出功率
低电流消耗
RX:19.9mA
低电源电压
2.3V 至 3.6V
无需外部中频滤波器
低中频接收器
所需的外部组件极少
小型尺寸
QFN 32 封装
无铅封装
数字 RSSI 和载波侦听指示器
数据速率高达 153.6kBaud
OOK、FSK 和 GFSK 数据调制
集成式位同步器
镜像抑制混频器
可编程频率以及 AFC 无需 TCXO 即可对晶体温度漂移进行补偿
适用于跳频系统
适用于符合
EN 300 220 标准、FCC CFR47 第 15 部分以及
ARIB STD-T67 标准的系统
用于生成 CC1020 配置数据的易用软件
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