5.9.6 Image Rejection Calibration

For perfect image rejection, the phase and gain of the “I” and “Q” parts of the analog RX chain must be perfectly matched. To improve the image rejection, the “I” and “Q” phase and gain difference can be fine-tuned by adjusting the PHASE_COMP and GAIN_COMP registers. This allows compensation for process variations and other nonidealities. The calibration is done by injecting a signal at the image frequency, and adjusting the phase and gain difference for minimum RSSI value.

During image rejection calibration, an unmodulated carrier should be applied at the image frequency (614.4 kHz below the desired channel). No signal should be present in the desired channel. The signal level should be 50 to 60 dB above the sensitivity in the desired channel, but the optimum level will vary from application to application. Too large input level gives poor results due to limited linearity in the analog IF chain, while too low input level gives poor results due to the receiver noise floor.

For best RSSI accuracy, use AGC_AVG[1:0] = 11 during image rejection calibration (RSSI value is averaged over 16 filter output samples). The RSSI register update rate then equals the receiver channel bandwidth (set in FILTER register) divided by 8, as the filter output rate is twice the receiver channel bandwidth. This gives the minimum waiting time between RSSI register reads (0.5 ms is used below). TI recommends the following image calibration procedure:

1. Define 3 variables: XP = 0, XG = 0 and DX = 64. Go to step 3.
2. Set DX = DX/2.
3. Write XG to GAIN_COMP register.
If XP + 2 × DX < 127, then write XP + 2 × DX to PHASE_COMP register else write 127 to PHASE_COMP register.
5. Wait at least 3 ms. Measure signal strength Y4 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
6. Write XP+DX to PHASE_COMP register.
7. Wait at least 3 ms. Measure signal strength Y3 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
8. Write XP to PHASE_COMP register.
9. Wait at least 3 ms. Measure signal strength Y2 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
10. Write XP-DX to PHASE_COMP register.
11. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
12. Write XP – 2 × DX to PHASE_COMP register.
13. Wait at least 3 ms. Measure signal strength Y0 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
14. Set AP = 2 × (Y0 – Y2 + Y4) – (Y1 + Y3).
If AP > 0 then set DP = ROUND ( 7 × DX × (2 × (Y0 – Y4) + Y1 – Y3) / (10 × AP)) else if Y0 + Y1 > Y3 + Y4 then set DP = DX else set DP = –DX.
If DP > DX then set DP = DX else if DP < –DX then set DP = –DX.
17. Set XP = XP + DP.
18. Write XP to PHASE_COMP register.
If XG + 2 × DX < 127 then write XG + 2 × DX to GAIN_COMP register else write 127 to GAIN_COMP register.
20. Wait at least 3 ms. Measure signal strength Y4 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
21. Write XG + DX to GAIN_COMP register.
22. Wait at least 3 ms. Measure signal strength Y3 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
23. Write XG to GAIN_COMP register.
24. Wait at least 3 ms. Measure signal strength Y2 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
25. Write XG – DX to GAIN_COMP register.
26. Wait at least 3 ms. Measure signal strength Y1 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
27. Write XG – 2 × DX to GAIN_COMP register.
28. Wait at least 3 ms. Measure signal strength Y0 as filtered average of 8 reads from RSSI register with 0.5 ms of delay between each RSSI read.
29. Set AG = 2 × (Y0 – Y2 + Y4) – (Y1 + Y3).
If AG > 0 then set DG = ROUND (7 × DX × (2 × (Y0 – Y4) + Y1 – Y3) / (10 × AG) else if Y0 + Y1 > Y3 + Y4 then set DG = DX else set DG = –DX.
If DG > DX then set DG = DX else if DG < –DX then set DG = –DX
32. Set XG = XG + DG.
33. If DX > 1 then go to step 2.
34. Write XP to PHASE_COMP register and XG to GAIN_COMP register.

If repeated calibration gives varying results, try to change the input level or increase the number of RSSI reads N. A good starting point is N = 8. As accuracy is more important in the last fine-calibration steps, it can be worthwhile to increase N for each loop iteration.

For high frequency deviation and high data rates (typically ≥ 76.8 kBaud), the analog filter succeeding the mixer must be bypassed by setting FILTER_BYPASS = 1 in the FILTER register. In this case the image rejection is degraded.

The image rejection is reduced for low supply voltages (typically < 2.5 V) when operating in the 402- to 470- MHz frequency range.