5.9.12 Automatic Power-up Sequencing

The CC1020 device has a built-in automatic power-up sequencing state machine. By setting the CC1020 device into this mode, the receiver can be powered-up automatically by a wake-up signal and will then check for a carrier signal (carrier sense). If carrier sense is not detected, it returns to power-down mode. A flow chart for automatic power-up sequencing is shown in Figure 5-16.

The automatic power-up sequencing mode is selected when PD_MODE[1:0] = 11 in the MAIN register. When the automatic power-up sequencing mode is selected, the functionality of the MAIN register is changed and used to control the sequencing.

By setting SEQ_PD = 1 in the MAIN register, the CC1020 device is set in power down mode. If SEQ_PSEL = 1 in the SEQUENCING register the automatic power-up sequence is initiated by a negative transition on the PSEL pin.

If SEQ_PSEL = 0 in the SEQUENCING register, then the automatic power-up sequence is initiated by a negative transition on the DIO pin (as long as SEP_DI_DO = 1 in the INTERFACE register).

Sequence timing is controlled through RX_WAIT[2:0] AND CS_WAIT[3:0] in the SEQUENCING register.

VCO and PLL calibration can also be done automatically as a part of the sequence. This is controlled through SEQ_CAL[1:0] in the MAIN register. Calibration can be done every time, every 16th sequence, every 256th sequence, or never. See Section 5.22.1 description for details. A description of when to do, and how the VCO and PLL self-calibration is done, is given in Section 5.12.2.

See also Application Note AN070 CC1020 Automatic Power-Up Sequencing (SWRA279).

1. Filter clock (FILTER_CLK): f_{filter_clock} = 2 × ChBW where ChBW is defined in Section 5.9.2.

2. ADC clock (ADC_CLK): where ADC_DIV[2:0] is set in the MODEM register.

Figure 5-16 Automatic Power-up Sequencing Flow Chart