ZHCSJU4I November 2006 – September 2018 CC1020
PRODUCTION DATA.
The top layer should be used for signal routing, and the open areas should be filled with metallization connected to ground using several vias.
The area under the chip is used for grounding and must be connected to the bottom ground plane with several vias. In the TI reference designs we have placed 9 vias inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migration of solder through the vias during the solder reflow process.
Do not place a via underneath the CC1020 device at “pin #1 corner” as this pin is internally connected to the exposed die attached pad, which is the main ground connection for the chip.
Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC1020 device supply pin. Supply power filtering is very important, especially for pins 23, 22, 20 and 18.
Each decoupling capacitor ground pad should be connected to the ground plane using a separate via. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary.
The external components should ideally be as small as possible and surface mount devices are highly recommended.
Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry.
A CC1020/1070DK reference design is available here: http://www.ti.com/tool/CC1020EMX_REFDES. It is strongly advised that this reference layout is followed very closely in order to get the best performance.