SWRS045F January   2006  – November 2018 CC1021

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Configuration
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  RF Transmit
    5. 4.5  RF Receive
    6. 4.6  RSSI / Carrier Sense
    7. 4.7  Intermediate Frequency (IF)
    8. 4.8  Crystal Oscillator
    9. 4.9  Frequency Synthesizer
    10. 4.10 Digital Inputs / Outputs
    11. 4.11 Current Consumption
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
      1. 5.3.1 Configuration Software
    4. 5.4  Microcontroller Interface
      1. 5.4.1 Configuration Interface
      2. 5.4.2 Signal Interface
      3. 5.4.3 PLL Lock Signal
    5. 5.5  4-wire Serial Configuration Interface
    6. 5.6  Signal Interface
      1. 5.6.1 Synchronous NRZ Mode
      2. 5.6.2 Transparent Asynchronous UART Mode
      3. 5.6.3 Synchronous Manchester Encoded Mode
        1. 5.6.3.1 Manchester Encoding and Decoding
    7. 5.7  Data Rate Programming
    8. 5.8  Frequency Programming
      1. 5.8.1 Dithering
    9. 5.9  Receiver
      1. 5.9.1  IF Frequency
      2. 5.9.2  Receiver Channel Filter Bandwidth
      3. 5.9.3  Demodulator, Bit Synchronizer and Data Decision
      4. 5.9.4  Receiver Sensitivity versus Data Rate and Frequency Separation
      5. 5.9.5  RSSI
      6. 5.9.6  Image Rejection Calibration
      7. 5.9.7  Blocking and Selectivity
      8. 5.9.8  Linear IF Chain and AGC Settings
      9. 5.9.9  AGC Settling
      10. 5.9.10 Preamble Length and Sync Word
      11. 5.9.11 Carrier Sense
      12. 5.9.12 Automatic Power-Up Sequencing
      13. 5.9.13 Automatic Frequency Control
      14. 5.9.14 Digital FM
    10. 5.10 Transmitter
      1. 5.10.1 FSK Modulation Formats
      2. 5.10.2 Output Power Programming
      3. 5.10.3 TX Data Latency
      4. 5.10.4 Reducing Spurious Emission and Modulation Bandwidth
    11. 5.11 Input and Output Matching and Filtering
    12. 5.12 Frequency Synthesizer
      1. 5.12.1 VCO, Charge Pump, and PLL Loop Filter
      2. 5.12.2 VCO and PLL Self-Calibration
      3. 5.12.3 PLL Turn-on Time versus Loop Filter Bandwidth
      4. 5.12.4 PLL Lock Time versus Loop Filter Bandwidth
    13. 5.13 VCO and LNA Current Control
    14. 5.14 Power Management
    15. 5.15 On-Off Keying (OOK)
    16. 5.16 Crystal Oscillator
    17. 5.17 Built-in Test Pattern Generator
    18. 5.18 Interrupt on Pin DCLK
      1. 5.18.1 Interrupt Upon PLL Lock
      2. 5.18.2 Interrupt Upon Received Signal Carrier Sense
    19. 5.19 PA_EN and LNA_EN Digital Output Pins
      1. 5.19.1 Interfacing an External LNA or PA
      2. 5.19.2 General-Purpose Output Control Pins
      3. 5.19.3 PA_EN and LNA_EN Pin Drive
    20. 5.20 System Considerations and Guidelines
      1. 5.20.1 SRD Regulations
      2. 5.20.2 Narrowband Systems
      3. 5.20.3 Low Cost Systems
      4. 5.20.4 Battery Operated Systems
      5. 5.20.5 High Reliability Systems
      6. 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS)
    21. 5.21 Antenna Considerations
    22. 5.22 Configuration Registers
      1. 5.22.1 Memory
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Input / Output Matching
      2. 6.2.2 Bias Resistor
      3. 6.2.3 PLL Loop Filter
      4. 6.2.4 Crystal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling and Filtering
    3. 6.3 PCB Layout Guidelines
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.5 RF Receive

All measurements were performed using the two-layer PCB CC1020EMX reference design. See Figure 6-1. The electrical specifications given for 868 MHz are also applicable for 902 to 928 MHz. TA = 25°C, AVDD = DVDD = 3.0 V, fC = 14.7456 MHz if nothing else stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Receiver Sensitivity, 433 MHz, FSK 38.4 kHz channel filter BW (1) –109 dBm Sensitivity is measured with PN9 sequence at BER = 10−3
(1) 38.4 kHz receiver channel filter bandwidth: 4.8 kBaud, NRZ coded data, ±4.95 kHz frequency deviation.
(2) 102.4 kHz receiver channel filter bandwidth: 19.2 kBaud, NRZ coded data, ±19.8 kHz frequency deviation.
(3) 102.4 kHz receiver channel filter bandwidth: 38.4 kBaud, NRZ coded data, ±19.8 kHz frequency deviation.
(4) 307.2 kHz receiver channel filter bandwidth: 153.6 kBaud, NRZ coded data, ±72 kHz frequency deviation.
See Table 5-6 and Table 5-7 or typical sensitivity figures at other channel filter bandwidths.
102.4 kHz channel filter BW (2) –104 dBm
102.4 kHz channel filter BW (3) –104 dBm
307.2 kHz channel filter BW (4) –96 dBm
Receiver Sensitivity, 868 MHz, FSK 38.4 kHz channel filter BW (1) –108 dBm
102.4 kHz channel filter BW (2) –103 dBm
102.4 kHz channel filter BW (3) –103 dBm
307.2 kHz channel filter BW (4) –94 dBm
Receiver sensitivity, 433 MHz, OOK 9.6 kBaud –103 dBm Manchester coded data.
See Table 5-14 for typical sensitivity figures at other data rates. Sensitivity is measured with PN9 sequence at
BER = 10−3
153.6 kBaud –81 dBm
Receiver sensitivity, 868 MHz, OOK 9.6 kBaud –104 dBm
153.6 kBaud –87 dBm
Saturation (maximum input level) FSK and OOK 10 dBm FSK: Manchester/NRZ coded data
OOK: Manchester coded data BER = 10−3
System noise bandwidth 38.4 to 307.2 kHz The receiver channel filter 6 dB bandwidth is programmable from 38.4 kHz to
307.2 kHz. See Section 5.9.2 for details.
Noise figure, cascaded 433 and 868 MHz 7 dB NRZ coded data
Input IP3(1) 433 MHz, 102.4 kHz
channel filter BW		 –23 dBm LNA2 maximum gain
–18 dBm LNA2 medium gain
–16 dBm LNA2 minimum gain
868 MHz, 102.4 kHz
channel filter BW		 –18 dBm LNA2 maximum gain
–15 dBm LNA2 medium gain
–13 dBm LNA2 minimum gain
Co-channel rejection, FSK and OOK 433 MHz and 868 MHz,
102.4 kHz channel filter BW		 –11 dB Wanted signal 3 dB above the sensitivity level, CW jammer at operating frequency, BER = 10−3
Adjacent channel rejection (ACR) 433 MHz,
102.4 kHz channel filter BW		 32 dB Measured at ±100 kHz offset.
See Figure 5-13 through Figure 5-16. Wanted signal 3 dB above the sensitivity level, CW jammer at adjacent channel, BER = 10−3.
868 MHz,
102.4 kHz channel filter BW		 30 dB
Image channel rejection 433/868 MHz No I/Q gain and phase calibration 25/25 dB Wanted signal 3 dB above the sensitivity level, CW jammer at image frequency, BER = 10−3.
102.4 kHz channel filter bandwidth. See Figure 5-13 through Figure 5-16.
Image rejection after calibration will depend on temperature and supply voltage. Refer to Section 5.9.6.
I/Q gain and phase calibrated 50/50 dB
Selectivity(2) 433 MHz,
102.4 kHz channel filter BW		 ±200 kHz offset 45 dB Wanted signal 3 dB above the sensitivity level. CW jammer is swept in 20 kHz steps within ±1 MHz from wanted channel.
BER = 10−3. Adjacent channel and image channel are excluded.
See Figure 5-13 through Figure 5-16.
±300 kHz offset 53 dB
868 MHz,
102.4 kHz channel filter BW		 ±200 kHz offset 45 dB
±300 kHz offset 50 dB
Blocking / Desensitization(3) 433/868 MHz ±1 MHz 52/58 dB Wanted signal 3 dB above the sensitivity level,
CW jammer at ±1, 2, 5 and 10 MHz offset,
BER = 10−3. 102.4 kHz channel filter bandwidth.
Complying with EN 300 220, class 2 receiver requirements.
±2 MHz 56/64 dB
±5 MHz 58/64 dB
±10 MHz 64/66 dB
Image frequency suppression 433/868 MHz No I/Q gain and phase calibration 35/35 dB Ratio between sensitivity for a signal at the image frequency to the sensitivity in the wanted channel.
Image frequency is RF− 2 IF. BER = 10−3.
102.4 kHz channel filter bandwidth.
I/Q gain and phase calibrated 60/60 dB
Spurious rejection 37 dB Ratio between sensitivity for an unwanted frequency to the sensitivity in the wanted channel. The signal source is swept over all frequencies 100 MHz to 2 GHz. Signal level for BER = 10−3. 102.4 kHz channel filter bandwidth.
LO leakage 433/868 MHz < –80/–66 dBm
VCO leakage –64 dBm VCO frequency resides between 1608 to 1880 MHz
Spurious emission, radiated CW 9 kHz to 1 GHz < –60 dBm Complying with EN 300 220 and FCC CFR47 part 15.
Spurious emissions can be measured as EIRP values according to EN 300 220.
1 to 4 GHz < –60 dBm
Input impedance 433 MHz 58 – j10 Ω Receive mode. See Section 5.11 for details.
868 MHz 54 – j22 Ω
Matched input impedance, S11 433 MHz –14 dB Using application circuit matching network. See Section 5.11 for details.
868 MHz –12 dB
Matched input impedance 433 MHz 39 – j14 Ω Using application circuit matching network. See Section 5.11 for details.
868 MHz 32 – j10 Ω
Bit synchronization offset 8000 ppm The maximum bit rate offset tolerated by the bit synchronization circuit for 6 dB degradation (synchronous modes only)
Data latency NRZ mode 4 Baud Time from clocking the data on the transmitter DIO pin until data is available on receiver DIO pin
Manchester mode 8 Baud
(1) Two tone test (+10 MHz and +20 MHz)
(2) Close-in spurious response rejection.
(3) Out-of-band spurious response rejection.
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