SWRS045F January 2006 – November 2018 CC1021
PRODUCTION DATA.
- 1Device Overview
- 2Revision History
- 3Terminal Configuration and Functions
-
4Specifications
- 4.1 Absolute Maximum Ratings
- 4.2 ESD Ratings
- 4.3 Recommended Operating Conditions
- 4.4 RF Transmit
- 4.5 RF Receive
- 4.6 RSSI / Carrier Sense
- 4.7 Intermediate Frequency (IF)
- 4.8 Crystal Oscillator
- 4.9 Frequency Synthesizer
- 4.10 Digital Inputs / Outputs
- 4.11 Current Consumption
- 4.12 Thermal Resistance Characteristics for VQFNP Package
-
5Detailed Description
- 5.1 Overview
- 5.2 Functional Block Diagram
- 5.3 Configuration Overview
- 5.4 Microcontroller Interface
- 5.5 4-wire Serial Configuration Interface
- 5.6 Signal Interface
- 5.7 Data Rate Programming
- 5.8 Frequency Programming
- 5.9
Receiver
- 5.9.1 IF Frequency
- 5.9.2 Receiver Channel Filter Bandwidth
- 5.9.3 Demodulator, Bit Synchronizer and Data Decision
- 5.9.4 Receiver Sensitivity versus Data Rate and Frequency Separation
- 5.9.5 RSSI
- 5.9.6 Image Rejection Calibration
- 5.9.7 Blocking and Selectivity
- 5.9.8 Linear IF Chain and AGC Settings
- 5.9.9 AGC Settling
- 5.9.10 Preamble Length and Sync Word
- 5.9.11 Carrier Sense
- 5.9.12 Automatic Power-Up Sequencing
- 5.9.13 Automatic Frequency Control
- 5.9.14 Digital FM
- 5.10 Transmitter
- 5.11 Input and Output Matching and Filtering
- 5.12 Frequency Synthesizer
- 5.13 VCO and LNA Current Control
- 5.14 Power Management
- 5.15 On-Off Keying (OOK)
- 5.16 Crystal Oscillator
- 5.17 Built-in Test Pattern Generator
- 5.18 Interrupt on Pin DCLK
- 5.19 PA_EN and LNA_EN Digital Output Pins
- 5.20 System Considerations and Guidelines
- 5.21 Antenna Considerations
- 5.22 Configuration Registers
- 6Applications, Implementation, and Layout
- 7Device and Documentation Support
- 8Mechanical Packaging and Orderable Information
5.12.1 VCO, Charge Pump, and PLL Loop Filter
The VCO is completely integrated and operates in the 1608 to 1880 MHz range. A frequency divider is used to get a frequency in the UHF range (402 to 470 and 804 to 930 MHz). The BANDSELECT bit in the ANALOG register selects the frequency band.
The VCO frequency is given by Equation 24.
The VCO frequency is divided by 2 and by 4 to generate frequencies in the two bands, respectively.
The VCO sensitivity (sometimes referred to as VCO gain) varies over frequency and operating conditions. Typically the VCO sensitivity varies between 12 and 36 MHz/V. For calculations the geometrical mean at 21 MHz/V can be used. The PLL calibration (explained below) measures the actual VCO sensitivity and adjusts the charge pump current accordingly to achieve correct PLL loop gain and bandwidth (higher charge pump current when VCO sensitivity is lower).
Equation 25 through Equation 29 can be used for calculating PLL loop filter component values, see Figure 6-1, for a desired PLL loop bandwidth, BW.
Define a minimum PLL loop bandwidth as shown in Equation 30.
If BWmin > Baud rate/3 then set BW = BWmin and if BWmin < Baud rate/3 then set BW = Baud rate/3 in Equation 25 through Equation 29.
There is one special case when using the recommended 14.7456 MHz crystal:
If the data rate is 4.8 kBaud or below the following loop filter components are recommended:
C6 = 100 nF
C7 = 3900 pF
C8 = 1000 pF
R2 = 2.2 kΩ
R3 = 6.8 kΩ
After calibration, the PLL bandwidth is set by the PLL_BW register in combination with the external loop filter components calculated above. The PLL_BW can be found from Equation 31.
Where: fref is the reference frequency (in MHz).
The PLL loop filter bandwidth increases with increasing PLL_BW setting.
After calibration, the applied charge pump current (CHP_CURRENT[3:0]) can be read in the STATUS1 register. The charge pump current is approximately given by Equation 32.
The combined charge pump and phase detector gain (in A/rad) is given by the charge pump current divided by 2π.
The PLL bandwidth will limit the maximum modulation frequency and hence, data rate.