SWRS037B January   2006  – March 2015 CC1150

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
    6. 4.6  RF Transmit
    7. 4.7  Crystal Oscillator
    8. 4.8  Frequency Synthesizer Characteristics
    9. 4.9  Analog Temperature Sensor
    10. 4.10 DC Characteristics
    11. 4.11 Power-On Reset
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
      1. 5.5.1 Chip Status Byte
      2. 5.5.2 Register Access
      3. 5.5.3 SPI Read
      4. 5.5.4 Command Strobes
      5. 5.5.5 FIFO Access
      6. 5.5.6 PATABLE Access
    6. 5.6  Microcontroller Interface and Pin Configuration
      1. 5.6.1 Configuration Interface
      2. 5.6.2 General Control and Status Pins
      3. 5.6.3 Optional Radio Control Feature
    7. 5.7  Data Rate Programming
    8. 5.8  Packet Handling Hardware Support
      1. 5.8.1 Data Whitening
      2. 5.8.2 Packet Format
        1. 5.8.2.1 Arbitrary Length Field Configuration
      3. 5.8.3 Packet Handling in Transmit Mode
      4. 5.8.4 Packet Handling in Firmware
    9. 5.9  Modulation Formats
      1. 5.9.1 Frequency Shift Keying
      2. 5.9.2 Minimum Shift Keying
      3. 5.9.3 Amplitude Modulation
    10. 5.10 Forward Error Correction with Interleaving
      1. 5.10.1 Forward Error Correction (FEC)
      2. 5.10.2 Interleaving
    11. 5.11 Radio Control
      1. 5.11.1 Power On Start-up Sequence
        1. 5.11.1.1 Automatic POR
        2. 5.11.1.2 Manual Reset
      2. 5.11.2 Crystal Control
      3. 5.11.3 Voltage Regulator Control
      4. 5.11.4 Active Mode
      5. 5.11.5 Timing
    12. 5.12 Data FIFO
    13. 5.13 Frequency Programming
    14. 5.14 VCO
      1. 5.14.1 VCO and PLL Self-Calibration
    15. 5.15 Voltage Regulators
    16. 5.16 Output Power Programming
      1. 5.16.1 Shaping and PA Ramping
    17. 5.17 General Purpose and Test Output Control Pins
    18. 5.18 Asynchronous and Synchronous Serial Operation
      1. 5.18.1 Asynchronous Serial Operation
      2. 5.18.2 Synchronous Serial Operation
    19. 5.19 System Considerations and Guidelines
      1. 5.19.1 SRD Regulations
      2. 5.19.2 Frequency Hopping and Multi-Channel Systems
      3. 5.19.3 Wideband Modulation Not Using Spread Spectrum
      4. 5.19.4 Data Burst Transmissions
      5. 5.19.5 Continuous Transmissions
      6. 5.19.6 Low-Cost Systems
      7. 5.19.7 Battery-Operated Systems
      8. 5.19.8 Increasing Output Power
    20. 5.20 Memory
      1. 5.20.1 Configuration Register Details
      2. 5.20.2 Status Register Details
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Bias Resistor
      2. 6.2.2 Balun and RF Matching
      3. 6.2.3 Crystal
      4. 6.2.4 Reference Signal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling
    3. 6.3 PCB Layout Recommendations
      1. 6.3.1 Package Description (QLP 16)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

3 Terminal Configuration and Functions

The CC1150 pinout is shown in Figure 3-1 and Table 3-1

CC1150 po_swrs037.gifFigure 3-1 Pinout Top View

3.1 Pin Attributes

Table 3-1 Pin Attributes(1)

PIN NO. PIN NAME TYPE DESCRIPTION
1 SCLK Digital Input Serial configuration interface, clock input.
2 SO (GDO1) Digital Output Serial configuration interface, data output.
Optional general output pin when CSn is high.
3 DVDD Power (Digital) 1.8-V to 3.6-V digital power supply for digital I/Os and for the digital core voltage regulator.
4 DCOUPL(2) Power (Digital) 1.6-V to 2.0-V digital power supply output for decoupling.
5 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input.
6 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
7 XOSC_Q2 Analog I/O Crystal oscillator pin 2.
8 GDO0
(ATEST)		 Digital I/O Digital output pin for general use:
  • Test signals
  • FIFO status signals
  • Clock output, down-divided from XOSC
  • Serial input TX data
Also used as analog test I/O for prototype/production testing.
9 CSn Digital Input Serial configuration interface, chip select.
10 RF_P RF I/O Positive RF output signal from PA.
11 RF_N RF I/O Negative RF output signal from PA.
12 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
13 AVDD Power (Analog) 1.8-V to 3.6-V analog power supply connection.
14 RBIAS Analog I/O External bias resistor for reference current.
15 DGUARD Power (Digital) Power supply connection for digital noise isolation.
16 SI Digital Input Serial configuration interface, data input.
(1) The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip.
(2) This pin is intended for use with the CC1150 only. It can not be used to provide supply voltage to other devices.
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