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SWRS121E July 2012 – January 2016 CC2560B , CC2564

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- MPQF282A

散热焊盘机械数据 (封装 | 引脚)

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5 Specifications

Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board (EVB). All specifications are over process, voltage, and temperature, unless otherwise indicated.

5.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise indicated). All parameters are measured as follows: VDD_IN = 3.6 V and VDD_IO = 1.8 V (unless otherwise indicated).

PARAMETERS		MIN	MAX	UNIT
Supply voltage range	VDD_IN	–0.5	4.8	V⁽²⁾
Supply voltage range	VDDIO_1.8V	–0.5	2.145	V
Input voltage to analog pins⁽³⁾		–0.5	2.1	V
Input voltage to all other pins		–0.5	VDD_IO + 0.5	V
Bluetooth RF inputs			10	dBm
Operating ambient temperature range, T_A⁽⁴⁾		–40	85	°C
Storage temperature range, T_stg		–55	125	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 7.1, Reference Design for Power and Radio Connections.

(3) Analog pins: BT_RF, XTALP, and XTALM

(4) The reference design supports a temperature range of –20°C to 70°C because of the operating conditions of the crystal.

5.1.1 ESD Ratings

			VALUE	UNIT
V_(ESD) electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±500	V
V_(ESD) electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22- ±YYY V C101⁽²⁾		±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.1.2 Power-On Hours

DEVICE	CONDITIONS	POWER-ON HOURS
CC256x	Duty cycle = 25% active and 75% sleep Tambient = 70ºC	15,400 (7 Years)

5.2 Recommended Operating Conditions

RATING	CONDITION	SYM	MIN	MAX	UNIT
Power supply voltage		VDD_IN	2.2	4.8	V
I/O power supply voltage		VDD_IO	1.62	1.92	V
High-level input voltage	Default	V_IH	0.65 x VDD_IO	VDD_IO	V
Low-level input voltage	Default	V_IL	0	0.35 x VDD_IO	V
I/O input rise and all times,10% to 90% — asynchronous mode		t_r and t_f	1	10	ns
I/O input rise and fall times, 10% to 90% — synchronous mode (PCM)			1	2.5	ns
Voltage dips on VDD_IN (V_BAT) duration = 577 μs to 2.31 ms, period = 4.6 ms				400	mV
Maximum ambient operating temperature⁽¹⁾ ⁽²⁾			–40	85	°C

(1) The device can be reliably operated for 7 years at T_ambient of 85°C, assuming 25% active mode and 75% sleep mode (15,400 cumulative active power-on hours).

(2) A crystal-based solution is limited by the temperature range required for the crystal to meet 20 ppm.

5.3 Power Consumption Summary

5.3.1 Static Current Consumption

OPERATIONAL MODE	TYP	MAX	UNIT
Shutdown mode⁽¹⁾	1	7	µA
Deep sleep mode⁽²⁾	40	105	µA
Total I/O current consumption in active mode		1	mA
Continuous transmission—GFSK⁽³⁾		107	mA
Continuous transmission—EDR⁽⁴⁾⁽⁵⁾		112.5	mA

(1) V_BAT + V_IO + V_SHUTDOWN

(2) V_BAT + V_IO

(3) At maximum output power (10 dBm)

(4) At maximum output power (8 dBm)

(5) Both π/4 DQPSK and 8DPSK

5.3.2 Dynamic Current Consumption

5.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 10-dBm output power

OPERATIONAL MODE	MASTER AND SLAVE	AVERAGE CURRENT	UNIT
Synchronous connection oriented (SCO) link HV3	Master and slave	13.7	mA
Extended SCO (eSCO) link EV3 64 kbps, no retransmission	Master and slave	13.2	mA
eSCO link 2-EV3 64 kbps, no retransmission	Master and slave	10	mA
GFSK full throughput: TX = DH1, RX = DH5	Master and slave	40.5	mA
EDR full throughput: TX = 2-DH1, RX = 2-DH5	Master and slave	41.2	mA
EDR full throughput: TX = 3-DH1, RX = 3-DH5	Master and slave	41.2	mA
Sniff, four attempt, 1.28 seconds	Master and slave	145	μA
Page or inquiry scan 1.28 seconds, 11.25 ms	Master and slave	320	μA
Page (1.28 seconds) and inquiry (2.56 seconds) scans, 11.25 ms	Master and slave	445	μA
A2DP source	Master	13.9	mA
A2DP sink	Master	15.2	mA
Assisted A2DP source	Master	16.9	mA
Assisted A2DP sink	Master	18.1	mA
Assisted WBS EV3; retransmit effort = 2; maximum latency = 8 ms	Master and slave	17.5 and 18.5	mA
Assisted WBS 2EV3; retransmit effort = 2; maximum latency = 12 ms	Master and slave	11.9 and 13	mA

5.3.2.2 Current Consumption for Different LE Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10-dBm output power

MODE		DESCRIPTION	AVERAGE CURRENT	UNIT
Advertising, nonconnectable		Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data	114	µA
Advertising, discoverable		Advertising in all three channels 1.28-seconds advertising interval 15 bytes advertise data	138	µA
Scanning		Listening to a single frequency per window 1.28-seconds scan interval 11.25-ms scan window	324	µA
Connected	Master role	500-ms connection interval 0-ms slave connection latency Empty TX and RX LL packets	169	µA
Connected	Slave role		199	µA

5.4 Electrical Characteristics

RATING			CONDITION	MIN	MAX	UNIT
High-level output voltage, V_OH			At 2, 4, 8 mA	0.8 x VDD_IO	VDD_IO	V
High-level output voltage, V_OH			At 0.1 mA	VDD_IO – 0.2	VDD_IO	V
Low-level output voltage, V_OL			At 2, 4, 8 mA	0	0.2 x VDD_IO	V
Low-level output voltage, V_OL			At 0.1 mA	0	0.2	V
I/O input impedance			Resistance	1		MΩ
I/O input impedance			Capacitance		5	pF
Output rise and fall times, 10% to 90% (digital pins)			C_L = 20 pF		10	ns
I/O pull currents	PCM-I2S bus, TX_DBG	PU	typ = 6.5	3.5	9.7	μA
	PCM-I2S bus, TX_DBG	PD	typ = 27	9.5	55
	All others	PU	typ = 100	50	300
	All others	PD	typ = 100	50	360

5.5 Timing and Switching Characteristics

5.5.1 Device Power Supply

The CC256x power-management hardware and software algorithms provide significant power savings, which is a critical parameter in an MCU-based system.

The power-management module is optimized for drawing extremely low currents.

5.5.1.1 Power Sources

The CC256x device requires two power sources:

VDD_IN: main power supply for the device
VDD_IO: power source for the 1.8-V I/O ring

The HCI module includes several on-chip voltage regulators for increased noise immunity and can be connected directly to the battery.

5.5.1.2 Device Power-Up and Power-Down Sequencing

The device includes the following power-up requirements (see Figure 5-1):

nSHUTD must be low. VDD_IN and VDD_IO are don't-care when nSHUTD is low. However, signals are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe. Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages with no VDD_IO and VDD_IN.
VDD_IO and VDD_IN must be stable before releasing nSHUTD.
The fast clock must be stable within 20 ms of nSHUTD going high.
The slow clock must be stable within 2 ms of nSHUTD going high.

The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to 100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case, ensure that the sequence and requirements are met.

CC2560A CC2560B CC2564 CC2564B SWRS098-008.gif

Figure 5-1 Power-Up and Power-Down Sequence

5.5.1.3 Power Supplies and Shutdown – Static States

The nSHUTD signal puts the device in ultra-low power mode and performs an internal reset to the device. The rise time for nSHUTD must not exceed 20 μs; nSHUTD must be low for a minimum of 5 ms.

To prevent conflicts with external signals, all I/O pins are set to the high-impedance (Hi-Z) state during shutdown and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in Section 4.1, Pin Attributes. Table 5-1 describes the static operation states.

Table 5-1 Power Modes

	VDD_IN ⁽¹⁾	VDD_IO⁽¹⁾	nSHUTD⁽¹⁾	PM_MODE	COMMENTS
1	None	None	Asserted	Shut down	I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
2	None	None	Deasserted	Not allowed	I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
3	None	Present	Asserted	Shut down	I/Os are defined as 3-state with internal pullup or pulldown enabled.
4	None	Present	Deasserted	Not allowed	I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
5	Present	None	Asserted	Shut down	I/O state is undefined.
6	Present	None	Deasserted	Not allowed	I/O state is undefined. No I/O voltages are allowed on nonfail-safe pins.
7	Present	Present	Asserted	Shut down	I/Os are defined as 3-state with internal pullup or pulldown enabled.
8	Present	Present	Deasserted	Active	See Section 5.5.1.4, I/O States in Various Power Modes

(1) The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a pulldown resistor, or left NC or floating (high-impedance output stage).

5.5.1.4 I/O States in Various Power Modes

CAUTION

Some device I/Os are not fail-safe (see Section 4.1, Pin Attributes). Fail-safe means that the pins do not draw current from an external voltage applied to the pin when I/O power is not supplied to the device. External voltages are not allowed on these I/O pins when the I/O supply voltage is not supplied because of possible damage to the device.

Table 5-2 lists the I/O states in various power modes.

Table 5-2 I/O States in Various Power Modes

I/O NAME	SHUT DOWN⁽¹⁾		DEFAULT ACTIVE⁽¹⁾		DEEP SLEEP⁽¹⁾
I/O NAME	I/O State	Pull	I/O State	Pull	I/O State	Pull
HCI_RX	Z	PU	I	PU	I	PU
HCI_TX	Z	PU	O-H		O
HCI_RTS	Z	PU	O-H		O
HCI_CTS	Z	PU	I	PU	I	PU
AUD_CLK	Z	PD	I	PD	I	PD
AUD_FSYNC	Z	PD	I	PD	I	PD
AUD_IN	Z	PD	I	PD	I	PD
AUD_OUT	Z	PD	Z	PD	Z	PD
TX_DBG	Z	PU	O

(1) I = input, O = output, Z = Hi-Z, — = no pull, PU = pullup, PD = pulldown, H = high, L = low

5.5.1.5 nSHUTD Requirements

PARAMETER	SYM	MIN	MAX	UNIT
Operation mode level ⁽¹⁾	V_IH	1.42	1.98	V
Shutdown mode level ⁽¹⁾	V_IL	0	0.4	V
Minimum time for nSHUT_DOWN low to reset the device		5		ms
Rise and fall times	t_r and t_f		20	μs

(1) An internal pulldown retains shut-down mode when no external signal is applied to this pin.

5.5.2 Clock Specifications

5.5.2.1 Slow Clock Requirements

An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V. The accuracy of the slow clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in the Bluetooth specification). The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of nSHUTD.

space

CHARACTERISTICS	CONDITION	SYM	MIN	TYP	MAX	UNIT
Input slow clock frequency				32768		Hz
Input slow clock accuracy (Initial + temp + aging)	Bluetooth				±250	ppm
Input slow clock accuracy (Initial + temp + aging)	ANT				±50	ppm
Input transition time t_r and t_f (10% to 90%)		t_r and t_f			200	ns
Frequency input duty cycle			15%	50%	85%
Slow clock input voltage limits	Square wave, DC-coupled	V_IH	0.65 × VDD_IO		VDD_IO	V peak
Slow clock input voltage limits	Square wave, DC-coupled	V_IL	0		0.35 × VDD_IO	V peak
Input impedance			1			MΩ
Input capacitance					5	pF

5.5.2.2 External Fast Clock Crystal Requirements and Operation

CHARACTERISTICS	CONDITION	SYM	MIN	TYP	MAX	UNIT
Supported crystal frequencies		f_in		26, 38.4		MHz
Frequency accuracy (Initial + temperature + aging)					±20	ppm
Crystal oscillator negative resistance	26 MHz, external capacitance = 8 pF		650	940		Ω
	I_osc = 0.5 mA		650	940
	26 MHz, external capacitance = 20 pF		490	710
	I_osc = 2.2 mA		490	710

5.5.2.3 Fast Clock Source Requirements (–40°C to +85°C)

CHARACTERISTICS	CONDITION		SYM	MIN	TYP	MAX	UNIT
Supported frequencies			F_REF	26, 38.4			MHz
Reference frequency accuracy	Initial + temp + aging					±20	ppm
Fast clock input voltage limits	Square wave, DC-coupled	V_IL		–0.2		0.37	V
	Square wave, DC-coupled	V_IH		1.0		2.1	V
	Sine wave, AC-coupled			0.4		1.6	V_p-p
	Sine wave, DC-coupled			0.4		1.6	V_p-p
	Sine wave input limits, DC-coupled			0.0		1.6	V
Fast clock input rise time (as % of clock period)	Square wave, DC-coupled					10%
Duty cycle				35%	50%	65%
Phase noise for 26 MHz	@ offset = 1 kHz					–123.4	dBc/Hz
	@ offset = 10 kHz					–133.4
	@ offset = 100 kHz					–138.4

5.5.3 Peripherals

5.5.3.1 UART

Figure 5-2 shows the UART timing diagram.

CC2560A CC2560B CC2564 CC2564B td_uart_wrs064.gif

Figure 5-2 UART Timing

Table 5-3 lists the UART timing characteristics.

Table 5-3 UART Timing Characteristics

SYMBOL	CHARACTERISTICS	CONDITION	MIN	TYP	MAX	UNIT
	Baud rate		37.5		4000	kbps
	Baud rate accuracy per byte	Receive and transmit	–2.5%		1.5%
	Baud rate accuracy per bit	Receive and transmit	–12.5%		12.5%
t3	CTS low to TX_DATA on		0	2		μs
t4	CTS high to TX_DATA off	Hardware flow control			1	byte
t6	CTS-high pulse width		1			bit
t1	RTS low to RX_DATA on		0	2		μs
t2	RTS high to RX_DATA off	Interrupt set to 1/4 FIFO			16	byte

Figure 5-3 shows the UART data frame.

CC2560A CC2560B CC2564 CC2564B td_uart2_wrs064.gif

Figure 5-3 Data Frame

Table 5-4 describes the symbols used in Figure 5-3.

Table 5-4 Data Frame Key

SYMBOL	DESCRIPTION
STR	Start bit
D0...Dn	Data bits (LSB first)
PAR	Parity bit (optional)
STP	Stop bit

5.5.3.2 PCM

Figure 5-4 shows the interface timing for the PCM.

CC2560A CC2560B CC2564 CC2564B td_aud_wrs064.gif

Figure 5-4 PCM Interface Timing

Table 5-5 lists the associated PCM master parameters.

Table 5-5 PCM Master

Symbol	PARAMETER	CONDITION	MIN	MAX	UNIT
T_clk	Cycle time		244.14 (4.096 MHz)	15625 (64 kHz)	ns
T_w	High or low pulse width		50% of T_clk min		ns
t_is	AUD_IN setup time		25		ns
t_ih	AUD_IN hold time		0		ns
t_op	AUD_OUT propagation time	40-pF load	0	10	ns
t_op	FSYNC_OUT propagation time	40-pF load	0	10	ns

Table 5-6 lists the associated PCM slave parameters.

Table 5-6 PCM Slave

SYMBOL	PARAMETER	CONDITION	MIN	MAX	UNIT
T_clk	Cycle time		66.67 (15 MHz)		ns
T_w	High or low pulse width		40% of T_clk		ns
T_is	AUD_IN setup time		8		ns
T_ih	AUD_IN hold time		0		ns
t_is	AUD_FSYNC setup time		8		ns
t_ih	AUD_FSYNC hold time		0		ns
t_op	AUD_OUT propagation time	40-pF load	0	21	ns

5.5.4 RF Performance

5.5.4.1 Bluetooth BR/EDR RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port.

5.5.4.1.1 Bluetooth Receiver—In-Band Signals

CHARACTERISTICS	CONDITION		MIN	TYP	MAX	BLUETOOTH SPECIFICATION	UNIT
Operation frequency range			2402		2480		MHz
Channel spacing				1			MHz
Input impedance				50			Ω
Sensitivity, dirty TX on⁽¹⁾	GFSK, BER = 0.1%		–91.5	–95		–70	dBm
	Pi/4-DQPSK, BER = 0.01%		–90.5	–94.5		–70
	8DPSK, BER = 0.01%		–81	–87.5		–70
BER error floor at sensitivity + 10dB, dirty TX off	Pi/4-DQPSK		1E–6	1E–7		1E–5
BER error floor at sensitivity + 10dB, dirty TX off	8DPSK		1E–6			1E–5
Maximum usable input power	GFSK, BER = 0.1%		–5			–20	dBm
	Pi/4-DQPSK, BER = 0.1%		–10
	8DPSK, BER = 0.1%		–10
Intermodulation characteristics	Level of interferers (for n = 3, 4, and 5)		–36	–30		–39	dBm
C/I performance⁽²⁾	GFSK, co-channel			8	10	11	dB
C/I performance⁽²⁾	EDR, co-channel	Pi/4-DQPSK		9.5	11	13
Image = –1 MHz	EDR, co-channel	8DPSK		16.5	20	21
Image = –1 MHz	GFSK, adjacent ±1 MHz			–10	–5	0
	EDR, adjacent ±1 MHz, (image)	Pi/4-DQPSK		–10	–5	0
	EDR, adjacent ±1 MHz, (image)	8DPSK		–5	–1	5
	GFSK, adjacent +2 MHz			–38	–35	–30
	EDR, adjacent, +2 MHz	Pi/4-DQPSK		–38	–35	–30
	EDR, adjacent, +2 MHz	8DPSK		–38	–30	–25
	GFSK, adjacent –2 MHz			–28	–20	–20
	EDR, adjacent –2 MHz	Pi/4-DQPSK		–28	–20	–20
	EDR, adjacent –2 MHz	8DPSK		–22	–13	–13
	GFSK, adjacent ≥ \|±3\| MHz			–45	–43	–40
	EDR, adjacent ≥ \|±3\| MHz	Pi/4-DQPSK		–45	–43	–40
	EDR, adjacent ≥ \|±3\| MHz	8DPSK		–44	–36	–33
RF return loss				–10			dB
RX mode LO leakage	Frf = (received RF – 0.6 MHz)			–63	–58		dBm

(1) Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast clock.

(2) Numbers show ratio of desired signal to interfering signal. Smaller numbers indicate better C/I performance.

5.5.4.1.2 Bluetooth Receiver—General Blocking

CHARACTERISTICS	CONDITION	TYP	UNIT
Blocking performance over full range, according to Bluetooth specification ⁽¹⁾	30 to 2000 MHz	–6	dBm
	2000 to 2399 MHz	–6
	2484 to 3000 MHz	–6
	3 to 12.75 GHz	–6

(1) Exceptions are taken out of the total 24 allowed in the Bluetooth specification.

5.5.4.1.3 Bluetooth Transmitter—GFSK

CHARACTERISTICS	MIN	TYP	MAX	BLUETOOTH SPECIFICATION	UNIT
Maximum RF output power⁽¹⁾	10	12			dBm
Power variation over Bluetooth band	–1		1		dB
Gain control range		30			dB
Power control step	2	5	8	2 to 8	dB
Adjacent channel power \|M–N\| = 2		–45	–39	≤ –20	dBm
Adjacent channel power \|M–N\| > 2		–50	–42	≤ –40	dBm

(1) To modify maximum output power, use an HCI VS command.

5.5.4.1.4 Bluetooth Transmitter—EDR

CHARACTERISTICS		MIN	TYP	MAX	BLUETOOTH SPECIFICATION	UNIT
Maximum RF output power⁽²⁾	Pi/4-DQPSK	6	8			dBm
Maximum RF output power⁽²⁾	8DPSK	6	8			dBm
Relative power		–2		1	–4 to +1	dB
Power variation over Bluetooth band		–1		1		dB
Gain control range			30			dB
Power control step		2	5	8	2 to 8	dB
Adjacent channel power \|M–N\| = 1			–36	–30	≤ –26	dBc
Adjacent channel power \|M–N\| = 2 ⁽¹⁾			–30	–23	≤ –20	dBm
Adjacent channel power \|M–N\| > 2 ⁽¹⁾			–42	–40	≤ –40	dBm

(1) Assumes 3-dB insertion loss from Bluetooth RF ball to antenna

(2) To modify maximum output power, use an HCI VS command.

5.5.4.1.5 Bluetooth Modulation—GFSK

CHARACTERISTICS	CONDITION		SYM	MIN	TYP	MAX	BLUETOOTH SPECIFICATION	UNIT
–20 dB bandwidth	GFSK				925	995	≤ 1000	kHz
Modulation characteristics	Δf1avg	Mod data = 4 1 s, 4 0 s: 111100001111...	F1 avg	150	165	170	140 to 175	kHz
	Δf2max ≥ limit for at least 99.9% of all Δf2max	Mod data = 1010101...	F2 max	115	130		> 115	kHz
	Δf2avg, Δf1avg			85%	88%		> 80%
Absolute carrier frequency drift	DH1			–25		25	< ±25	kHz
Absolute carrier frequency drift	DH3 and DH5			–35		35	< ±40	kHz
Drift rate						15	< 20	kHz/ 50 μs
Initial carrier frequency tolerance	f0 – fTX			–75		+75	< ±75	kHz

5.5.4.1.6 Bluetooth Modulation—EDR

CHARACTERISTICS	CONDITION	TYP	MAX	BLUETOOTH SPECIFICATION	UNIT
Carrier frequency stability			±5	≤ 10	kHz
Initial carrier frequency tolerance			±75	±75	kHz
RMS DEVM ⁽¹⁾	Pi/4-DQPSK	6%	15%	20%
RMS DEVM ⁽¹⁾	8DPSK	6%	13%	13%
99% DEVM⁽¹⁾	Pi/4-DQPSK		30%	30%
99% DEVM⁽¹⁾	8DPSK		20%	20%
Peak DEVM ⁽¹⁾	Pi/4-DQPSK	14%	30%	35%
Peak DEVM ⁽¹⁾	8DPSK	16%	25%	25%

(1) Max performance refers to maximum TX power.

5.5.4.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions

CHARACTERISTICS	CONDITION	TYP	MAX	UNIT
Second harmonic⁽¹⁾	Measured at maximum output power	–14	–2	dBm
Third harmonic⁽¹⁾		–10	–6	dBm
Fourth harmonics⁽¹⁾		–19	–11	dBm

(1) Meets FCC and ETSI requirements with external filter shown in Figure 7-1

5.5.4.2 Bluetooth LE RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port.

5.5.4.2.1 BLE Receiver—In-Band Signals

CHARACTERISTIC	CONDITION	MIN	TYP	MAX	BLE SPECIFICATION	UNIT
Operation frequency range		2402		2480		MHz
Channel spacing			2			MHz
Input impedance			50			Ω
Sensitivity, dirty TX on⁽¹⁾	PER = 30.8%; dirty TX on	–93	–96		≤ –70	dBm
Maximum usable input power	GMSK, PER = 30.8%	–5			≥ –10	dBm
Intermodulation characteristics	Level of interferers (for n = 3, 4, 5)	–36	–30		≥ –50	dBm
C/I performance⁽²⁾ Image = –1 MHz	GMSK, co-channel		8	12	≤ 21	dB
	GMSK, adjacent ±1 MHz		–5	0	≤ 15
	GMSK, adjacent +2 MHz		–45	–38	≤ –17
	GMSK, adjacent –2 MHz		–22	–15	≤ –15
	GMSK, adjacent ≥ \|±3\| MHz		–47	–40	≤ –27
RX mode LO leakage	Frf = (received RF – 0.6 MHz)		–63	–58		dBm

(1) Sensitivity degradation up to 3 dB may occur where the BLE frequency is a harmonic of the fast clock.

(2) Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance.

5.5.4.2.2 BLE Receiver—General Blocking

CHARACTERISTICS	CONDITION	TYP	BLE SPECIFICATION	UNIT
Blocking performance over full range, according to BLE specification⁽¹⁾	30 to 2000 MHz	–15	≥ –30	dBm
	2000 to 2399 MHz	–15	≥ –35
	2484 to 3000 MHz	–15	≥ –35
	3 to 12.75 GHz	–15	≥ –30

(1) Exceptions are taken out of the total 10 allowed in the BLE specification.

5.5.4.2.3 BLE Transmitter

CHARACTERISTICS	MIN	TYP	MAX	BLE SPECIFICATION	UNIT
Maximum RF output power⁽²⁾	10	12⁽¹⁾		≤10	dBm
Power variation over BLE band	–1		1		dB
Adjacent channel power \|M-N\| = 2		–45	–39	≤ –20	dBm
Adjacent channel power \|M-N\| > 2		–50	–42	≤ –30	dBm

(1) To achieve the BLE specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna. Otherwise, use an HCI VS command to modify the output power.

(2) To modify maximum output power, use an HCI VS command.

5.5.4.2.4 BLE Modulation

CHARACTERISTICS	CONDITION		SYM	MIN	TYP	MAX	BLE SPEC.	UNIT
Modulation characteristics	Δf1avg	Mod data = 4 1s, 4 0 s: 1111000011110000...	Δf1 avg	240	250	260	225 to 275	kHz
	Δf2max ≥ limit for at least 99.9% of all Δf2max	Mod data = 1010101...	Δf2 max	185	210		≥ 185	kHz
	Δf2avg, Δf1avg			0.85	0.9		≥ 0.8
Absolute carrier frequency drift				–25		25	≤ ±50	kHz
Drift rate						15	≤ 20	kHz/50 ms
Initial carrier frequency tolerance				–75		75	≤ ±100	kHz

5.5.4.2.5 BLE Transceiver, Out-Of-Band and Spurious Emissions

See Section 5.5.4.1.7, Bluetooth Transmitter, Out-of-Band and Spurious Emissions.

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5 Specifications

5.1 Absolute Maximum Ratings(1)

5.1.1 ESD Ratings

5.1.2 Power-On Hours

5.2 Recommended Operating Conditions

5.3 Power Consumption Summary

5.3.1 Static Current Consumption

5.3.2 Dynamic Current Consumption

5.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios

5.3.2.2 Current Consumption for Different LE Scenarios

5.4 Electrical Characteristics

5.5 Timing and Switching Characteristics

5.5.1 Device Power Supply

5.5.1.1 Power Sources

5.5.1.2 Device Power-Up and Power-Down Sequencing

5.5.1.3 Power Supplies and Shutdown – Static States

Table 5-1 Power Modes

5.5.1.4 I/O States in Various Power Modes

Table 5-2 I/O States in Various Power Modes

5.5.1.5 nSHUTD Requirements

5.5.2 Clock Specifications

5.5.2.1 Slow Clock Requirements

5.5.2.2 External Fast Clock Crystal Requirements and Operation

5.5.2.3 Fast Clock Source Requirements (–40°C to +85°C)

5.5.3 Peripherals

5.5.3.1 UART

Table 5-3 UART Timing Characteristics

Table 5-4 Data Frame Key

5.5.3.2 PCM

Table 5-5 PCM Master

Table 5-6 PCM Slave

5.5.4 RF Performance

5.5.4.1 Bluetooth BR/EDR RF Performance

5.5.4.1.1 Bluetooth Receiver—In-Band Signals

5.5.4.1.2 Bluetooth Receiver—General Blocking

5.5.4.1.3 Bluetooth Transmitter—GFSK

5.5.4.1.4 Bluetooth Transmitter—EDR

5.5.4.1.5 Bluetooth Modulation—GFSK

5.5.4.1.6 Bluetooth Modulation—EDR

5.5.4.1.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions

5.5.4.2 Bluetooth LE RF Performance

5.5.4.2.1 BLE Receiver—In-Band Signals

5.5.4.2.2 BLE Receiver—General Blocking

5.5.4.2.3 BLE Transmitter

5.5.4.2.4 BLE Modulation

5.5.4.2.5 BLE Transceiver, Out-Of-Band and Spurious Emissions

5.1 Absolute Maximum Ratings⁽¹⁾