ZHCSKG5C October 2019 – April 2024 CC2652P
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Core Current Consumption | ||||||
Icore | Reset and Shutdown | Reset. RESET_N pin asserted or VDDS below power-on-reset threshold | 150 | nA | ||
Shutdown. No clocks running, no retention | 150 | |||||
Standby without cache retention | RTC running, CPU, 80kB RAM and (partial) register retention. RCOSC_LF | 0.94 | µA | |||
RTC running, CPU, 80kB RAM and (partial) register retention XOSC_LF | 1.09 | µA | ||||
Standby with cache retention | RTC running, CPU, 80kB RAM and (partial) register retention. RCOSC_LF | 3.2 | µA | |||
RTC running, CPU, 80kB RAM and (partial) register retention. XOSC_LF | 3.3 | µA | ||||
Idle | Supply Systems and RAM powered RCOSC_HF | 675 | µA | |||
Active | MCU running CoreMark at 48MHz RCOSC_HF | 3.39 | mA | |||
Peripheral Current Consumption(1), (2) | ||||||
Iperi | Peripheral power domain | Delta current with domain enabled | 97.7 | µA | ||
Serial power domain | Delta current with domain enabled | 7.2 | ||||
RF Core | Delta current with power domain enabled, clock enabled, RF core idle | 210.9 | ||||
µDMA | Delta current with clock enabled, module is idle | 63.9 | ||||
Timers | Delta current with clock enabled, module is idle(5) | 81.0 | ||||
I2C | Delta current with clock enabled, module is idle | 10.1 | ||||
I2S | Delta current with clock enabled, module is idle | 26.3 | ||||
SSI | Delta current with clock enabled, module is idle | 82.9 | ||||
UART | Delta current with clock enabled, module is idle(3) | 167.5 | ||||
CRYPTO (AES) | Delta current with clock
enabled, module is idle(4) | 25.6 | ||||
PKA | Delta current with clock enabled, module is idle | 84.7 | ||||
TRNG | Delta current with clock enabled, module is idle | 35.6 | ||||
Sensor Controller Engine Consumption | ||||||
ISCE | Active mode | 24MHz, infinite loop | 808.5 | µA | ||
Low-power mode | 2MHz, infinite loop | 30.1 |