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ZHCSM59B November 2014 – September 2020 CC3100MOD

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

#SWAS0317086 shows the host SPI timing diagram.

Figure 8-8 Host SPI Timing

Table 8-2 Host SPI Interface Timing Parameters

PARAMETER NUMBER	DESCRIPTION		MIN	MAX	UNIT
I1	F#SWAS032469401	Clock frequency at V_BAT = 3.3 V		20	MHz
I1	F#SWAS032469401	Clock frequency at V_BAT ≤ 2.1 V		12	MHz
I2	t_clk#SWAS032469401 #SWAS0319151	Clock period	50		ns
I5	D#SWAS032469401	Duty cycle	45%	55%
I6	t_IS#SWAS032469401	RX data setup time	4		ns
I7	t_IH#SWAS032469401	RX data hold time	4		ns
I8	t_OD#SWAS032469401	TX data output delay		20	ns
I9	t_OH#SWAS032469401	TX data hold time		24	ns

(1) The timing parameter has a maximum load of 20 pf at 3.3 V.

(2) Ensure that nCS (active-low signal) is asserted 10 ns before the clock is toggled. The nCS signal can be deasserted 10 ns after the clock edge.