The hibernate mode is the lowest power mode in which all of the digital logic is power-gated. Only a small section of the logic powered directly by the main input supply is retained. The real-time clock (RTC) is kept running and the module wakes up when the n_HIB line is asserted by the host driver. The typical battery drain in this mode is 5 µA. The wake-up time is longer than LPDS mode at about 50 ms.