米6体育平台手机版

ZHCSCJ7E July 2013 – June 2014 CC3200

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGC|64
- MPQF125F

散热焊盘机械数据 (封装 | 引脚)

RGC|64
- QFND481

订购信息

4 Specifications

All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over process and voltage, unless otherwise indicated.

4.0.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

PARAMETERS	PINS	MIN	MAX	UNIT
V_BAT and V_IO	37, 39, 44	–0.5	3.8	V
V_IO-V_BAT (differential)	10, 54		0.0	V
Digital inputs		–0.5	V_IO + 0.5	V
RF pins		–0.5	2.1	V
Analog pins (XTAL)		–0.5	2.1	V
Operating temperature range (T_A )		–40	+85	°C

4.0.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–55	+125	°C
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2000	+2000	V
V_ESD	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	+500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.0.3 Power-On Hours

CONDITIONS		POH
T_Ambient up to 85°C, assuming 20% active mode and 80% sleep mode		17,500⁽¹⁾

(1) The CC3200 device can be operated reliably for 10 years.

4.0.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

PARAMETERS	PINS	CONDITIONS⁽²⁾⁽³⁾	MIN	TYP	MAX	UNIT
V_BAT, V_IO (shorted to V_BAT)	10, 37, 39, 44, 54	Direct battery connection	2.1	3.3	3.6	V
V_BAT, V_IO (shorted to V_BAT)	10, 37, 39, 44, 54	Preregulated 1.85 V	1.76	1.85	1.9	V
Ambient thermal slew			–20		20	°C/minute

(1) Operating temperature is limited by crystal frequency variation.

(2) To ensure WLAN performance, ripple on the 2.1- to 3.3-V supply must be less than ±300 mV.

(3) To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV).

The device enters a brown-out condition whenever the input voltage dips below V_BROWN (see Figure 4-1). This condition must be considered during design of the power supply routing, especially if operating from a battery. High-current operations (such as a TX packet) cause a dip in the supply voltage, potentially triggering a brown-out. The resistance includes the internal resistance of the battery, contact resistance of the battery holder (4 contacts for a 2 x AA battery) and the wiring and PCB routing resistance.

Note: For V_BAT wide-voltage mode, V_BROWN = 2.1 V. For preregulated 1.85-V mode, V_BROWN = 1.76 V.

Figure 4-1 Brown-Out Timing Diagram

For example, the device draws about 400 mA from the supply @ 2.3 V for a 1 DSSS packet at maximum power. This condition can cause a drop of 200 mV across a 0.5-Ω routing resistance.

In the brown-out condition, the device is in RESET state except for the Hibernate module (including the 32-kHz RTC clock), which is kept on. The current in this state can reach approximately 400 µA.

4.0.5 Electrical Characteristics

3.3 V, 25°C

GPIO Pins Except 29, 30, 45, 50, 52, and 53 (25°C)⁽¹⁾
PARAMETER			TEST CONDITIONS	MIN	NOM	MAX	UNIT
C_IN	Pin capacitance				4		pF
V_IH	High-level input voltage			0.65 × VDD		VDD + 0.5 V	V
V_IL	Low-level input voltage			–0.5		0.35 × VDD	V
I_IH	High-level input current				5		nA
I_IL	Low-level input current				5		nA
V_OH	High-level output voltage (VDD = 3.0 V)			2.4			V
V_OL	Low-level output voltage (VDD = 3.0 V)					0.4	V
I_OH	High-level source current, VOH = 2.4	2-mA Drive		2			mA
		4-mA Drive		4			mA
		6-mA Drive		6			mA
I_OL	Low-level sink current, VOH = 0.4	2-mA Drive		2			mA
		4-mA Drive		4			mA
		6-mA Drive		6			mA

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of interference to the WLAN radio and mitigates any potential degradation of RF sensitivity and performance. The default drive strength setting is 6 mA.

3.3 V, 25°C

GPIO Pins 29, 30, 45, 50, 52, and 53 (25°C)⁽¹⁾
PARAMETER			TEST CONDITIONS	MIN	NOM	MAX	UNIT
C_IN	Pin capacitance				7		pF
V_IH	High-level input voltage			0.65 × VDD		VDD + 0.5V	V
V_IL	Low-level input voltage			–0.5		0.35 × VDD	V
I_IH	High-level input current				50		nA
I_IL	Low-level input current				50		nA
V_OH	High-level output voltage (VDD= 3.0 V)			2.4			V
V_OL	Low-level output voltage (VDD= 3.0 V)					0.4	V
I_OH	High-level source current, V_OH = 2.4	2-mA Drive		1.5			mA
		4-mA Drive		2.5			mA
		6-mA Drive		3.5			mA
I_OL	Low-level sink current, V_OH = 0.4	2-mA Drive		1.5			mA
		4-mA Drive		2.5			mA
		6-mA Drive		3.5			mA

3.3 V, 25°C

Pin Internal Pullup and Pulldown (25°C)⁽¹⁾
PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
I_OH	Pull-Up current, V_OH = 2.4 (VDD = 3.0 V)		5		10	µA
I_OL	Pull-Down current, V_OL = 0.4 (VDD = 3.0 V)		5			µA

(1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of interference to WLAN radio and mitigates any potential degradation of RF sensitivity and performance. The default drive-strength setting is 6 mA.

4.0.6 WLAN Receiver Characteristics

T_A = +25°C, V_BAT = 2.1 to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz)

Parameter	Condition (Mbps)	Typ	Units
Sensitivity (8% PER for 11b rates, 10% PER for 11g/11n rates)(10% PER)⁽²⁾	1 DSSS	–95.7	dBm
	2 DSSS	–93.6
	11 CCK	–88.0
	6 OFDM	–90.0
	9 OFDM	–89.0
	18 OFDM	–86.0
	36 OFDM	–80.5
	54 OFDM	–74.0
	MCS0 (GF)⁽¹⁾	–89.0
	MCS7 (GF)⁽¹⁾	–71.0
Maximum input level (10% PER)	802.11b	–4.0
Maximum input level (10% PER)	802.11g	–10.0

(1) Sensitivity for mixed mode is 1-dB worse.

(2) Sensitivity is 1-dB worse on channel 13 (2472 MHz).

4.0.7 WLAN Transmitter Characteristics

T_A = +25°C, V_BAT = 2.1 to 3.6 V. Parameters measured at SoC pin on channel 7 (2442 MHz).⁽¹⁾

Parameter	Condition⁽²⁾	Min	Typ	Max	Units
Maximum RMS output power measured at 1 dB from IEEE spectral mask or EVM	1 DSSS		18.0		dBm
	2 DSSS		18.0
	11 CCK		18.3
	6 OFDM		17.3
	9 OFDM		17.3
	18 OFDM		17.0
	36 OFDM		16.0
	54 OFDM		14.5
	MCS7 (MM)		13.0
Transmit center frequency accuracy		–25		25	ppm

(1) Channel-to-channel variation is up to 2 dB. The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits.

(2) In preregulated 1.85-V mode, maximum TX power is 0.25 to 0.75 dB lower for modulations higher than 18 OFDM.

4.0.8 Current Consumption

T_A = +25°C, V_BAT = 3.6 V

PARAMETER		TEST CONDITIONS⁽¹⁾⁽⁶⁾			TYP	UNIT
MCU ACTIVE	NWP ACTIVE	TX	1 DSSS	TX power level = 0	278	mA
			1 DSSS	TX power level = 4	194
			6 OFDM	TX power level = 0	254
			6 OFDM	TX power level = 4	185
			54 OFDM	TX power level = 0	229
			54 OFDM	TX power level = 4	166
		RX	1 DSSS		59
		RX	54 OFDM		59
	NWP idle connected⁽³⁾				15.3
MCU SLEEP	NWP ACTIVE	TX	1 DSSS	TX power level = 0	275	mA
			1 DSSS	TX power level = 4	191
			6 OFDM	TX power level = 0	251
			6 OFDM	TX power level = 4	182
			54 OFDM	TX power level = 0	226
			54 OFDM	TX power level = 4	163
		RX	1 DSSS		56
		RX	54 OFDM		56
	NWP idle connected⁽³⁾				12.2
MCU LPDS	NWP active	TX	1 DSSS	TX power level = 0	272	mA
			1 DSSS	TX power level = 4	188
			6 OFDM	TX power level = 0	248
			6 OFDM	TX power level = 4	179
			54 OFDM	TX power level = 0	223
			54 OFDM	TX power level = 4	160
		RX	1 DSSS		53
		RX	54 OFDM		53
	NWP LPDS⁽²⁾				0.12
	NWP idle connected⁽³⁾				0.695
MCU hibernate	NWP hibernate⁽⁴⁾				4	µA
Peak calibration current ⁽⁵⁾		V_BAT= 3.3 V			450	mA
		V_BAT= 2.1 V			670
		V_BAT= 1.85 V			700

(1) TX power level = 0 implies maximum power (see Figure 4-2 through Figure 4-4). TX power level = 4 implies output power backed off approximately 4 dB.

(2) LPDS current does not include the external serial flash. The LPDS number reported is with retention of 64KB MCU SRAM. The CC3200 device can be configured to retain 0KB, 64KB, 128KB, 192KB or 256KB SRAM in LPDS. Each 64KB retained increases LPDS current by 4 µA.

(3) DTIM = 1

(4) Serial flash current consumption in power-down mode during hibernate is not included.

(5) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms . Calibration is performed sparingly, typically when coming out of Hibernate and only if temperature has changed by more than 20°C or the time elapsed from prior calibration is greater than 24 hours.

(6) The CC3200 system is a constant power-source system. The active current numbers scale based on the V_BAT voltage supplied.

Note: The area enclosed in the circle represents a significant reduction in current when transitioning from TX power level 3 to 4. In the case of lower range requirements (14 dbm output power), TI recommends using TX power level 4 to reduce the current.

Figure 4-2 TX Power and IBAT vs TX Power Level Settings (1 DSSS)

Figure 4-3 TX Power and IBAT vs TX Power Level Settings (6 OFDM)

Figure 4-4 TX Power and IBAT vs TX Power Level Settings (54 OFDM)

4.0.9 Thermal Characteristics for RGC Package

AIR FLOW
PARAMETER	0 lfm (C/W)	150 lfm (C/W)	250 lfm (C/W)	500 lfm (C/W)
θ_ja	23	14.6	12.4	10.8
Ψ_jt	0.2	0.2	0.3	0.1
Ψ_jb	2.3	2.3	2.2	2.4
θ_jc	6.3
θ_jb	2.4

4.1 Timing and Switching Characteristics

4.1.1 Power Supply Sequencing

For proper operation of the CC3200 device, perform the recommended power-up sequencing as follows:

Tie V_BAT (pins 37, 39, 44) and V_IO (pins 54 and 10) together on the board.
Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit (100K || 0.1 µF, RC = 10 ms).
For an external RTC clock, ensure that the clock is stable before RESET is deasserted (high).

For timing diagrams, see Section 4.1.2, Reset Timing.

4.1.2 Reset Timing

4.1.2.1 nRESET (32K XTAL)

Figure 4-5 shows the reset timing diagram for the 32K XTAL first-time power-up and reset removal.

Figure 4-5 First-Time Power-Up and Reset Removal Timing Diagram (32K XTAL)

Table 4-1 describes the timing requirements for the 32K XTAL first-time power-up and reset removal.

Table 4-1 First-Time Power-Up and Reset Removal Timing Requirements (32K XTAL)

Item	Name	Description	Typ
T1	Supply settling time	Depends on application board power supply, decap, and so on	3 ms
T2	Hardware wakeup time		25 ms
T3	Time taken by ROM firmware to initialize hardware	Includes 32.768 -kHz XOSC settling time	1.1 s

4.1.2.2 nRESET (External 32K)

Figure 4-6 shows the reset timing diagram for the external 32K first-time power-up and reset removal.

Figure 4-6 First-Time Power-Up and Reset Removal Timing Diagram (External 32K)

Table 4-2 describes the timing requirements for the external 32K first-time power-up and reset removal.

Table 4-2 First-Time Power-Up and Reset Removal Timing Requirements (External 32K)

Item	Name	Description	Typ
T1	Supply settling time	Depends on application board power supply, decap, and so on	3 ms
T2	Hardware wakeup time		25 ms
T3	Time taken by ROM firmware to initialize hardware	Time taken by ROM firmware	3 ms

4.1.2.3 Wakeup from Hibernate

Figure 4-7 shows the timing diagram for wakeup from the hibernate state.

Figure 4-7 nHIB Timing Diagram

NOTE

The 32.768-kHz XTAL is kept enabled by default when the chip goes to hibernate.

Table 4-3 describes the timing requirements for nHIB.

Table 4-3 Software Hibernate Timing Requirements

Item	Name	Description	Min	Typ	Max
T_{hib_min}	Minimum hibernate time		10 ms
T_{wake_from_hib}⁽¹⁾	Hardware wakeup time plus firmware initialization time			50 ms

(1) Twake_from_hib can be 200 ms on rare occasions when calibration is performed. Calibration is performed sparingly, typically when exiting Hibernate and only if temperature has changed by more than 20°C or more than 24 hours have elapsed since a prior calibration.

4.1.3 Clock Specifications

The CC3200 device requires two separate clocks for its operation:

A slow clock running at 32.768 kHz is used for the RTC.
A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem.

The device features internal oscillators that enable the use of cheaper crystals rather than dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and reduce overall cost.

4.1.3.1 Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance.

Figure 4-8 shows the crystal connections for the slow clock.

Figure 4-8 RTC Crystal Connections

4.1.3.2 Slow Clock Using an External Clock

When an RTC clock oscillator is present in the system, the CC3200 device can accept this clock directly as an input. The clock is fed on the RTC_XTAL_P line and the RTC_XTAL_N line is held to VIO. The clock must be a CMOS-level clock compatible with VIO fed to the device.

Figure 4-9 shows the external RTC clock input connection.

Figure 4-9 External RTC Clock Input

4.1.3.3 Fast Clock (F_ref) Using an External Crystal

The CC3200 device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The XTAL is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading capacitors.

Figure 4-10 shows the crystal connections for the fast clock.

Figure 4-10 Fast Clock Crystal Connections

4.1.3.4 Fast Clock (F_ref) Using an External Oscillator

The CC3200 device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system.

If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the LDO improves noise on the TCXO power supply.

Figure 4-11 shows the connection.

Figure 4-11 External TCXO Input

Table 4-4 lists the external F_ref clock requirements.

Table 4-4 External F_ref Clock Requirements (–40°C to +85°C)

Characteristics		Condition	Sym	Min	Typ	Max	Unit
Frequency					40.00		MHz
Frequency accuracy (Initial + temp + aging)						±20	ppm
Frequency input duty cycle				45	50	55	%
Clock voltage limits		Sine or clipped sine wave, AC coupled	Vpp	0.7		1.2	Vpp
Phase noise @ 40 MHz		@ 1 kHz				–125	dBc/Hz
		@ 10 kHz				–138.5	dBc/Hz
		@ 100 kHz				–143	dBc/Hz
Input impedance	Resistance			12			KΩ
Input impedance	Capacitance					7	pF

4.1.3.5 Input Clocks/Oscillators

Table 4-5 lists the RTC crystal requirements.

Table 4-5 RTC Crystal Requirements

CHARACTERISTICS	CONDITION	TYP	MAX	UNIT
Frequency		32.768		kHz
Frequency accuracy	Initial + temp + aging		±150	ppm
Crystal ESR	32.768 kHz, C1 = C2 = 10 pF		70	kΩ

Table 4-6 lists the external RTC digital clock requirements.

Table 4-6 External RTC Digital Clock Requirements

CHARACTERISTICS	CONDITION	SYM	MIN	TYP	MAX	UNIT
Frequency				32768		Hz
Frequency accuracy					±150	ppm
(Initial + temp + aging)					±150	ppm
Input transition time t_r/t_f (10% to 90%)		t_r/t_f			100	ns
Frequency input duty cycle			20	50	80	%
Slow clock input voltage limits	Square wave, DC coupled	V_ih	0.65 × V_IO		V_IO	V
Slow clock input voltage limits	Square wave, DC coupled	V_il	0		0.35 × V_IO	V peak
Input impedance			1			MΩ
Input impedance					5	pF

Table 4-7 lists the WLAN fast-clock crystal requirements.

Table 4-7 WLAN Fast-Clock Crystal Requirements

CHARACTERISTICS	CONDITION	MIN	TYP	MAX	UNIT
Frequency			40		MHz
Frequency accuracy	Initial + temp + aging			±20	ppm
Crystal ESR	40 MHz, C1 = C2 = 6.2 pF	40	50	60	Ohm

4.1.4 Peripherals

This section describes the peripherals that are supported by the CC3200 device:

SPI
McASP
GPIO
I²C
IEEE 1149.1 JTAG
ADC
Camera parallel port
UART

4.1.4.1 SPI

4.1.4.1.1 SPI Master

The CC3200 microcontroller includes one SPI module, which can be configured as a master or slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase, a programmable timing control between chip select and external clock generation, and a programmable delay before the first SPI word is transmitted. Slave mode does not include a dead cycle between two successive words.

Figure 4-12 shows the timing diagram for the SPI master.

Figure 4-12 SPI Master Timing Diagram

Table 4-8 lists the timing parameters for the SPI master.

Table 4-8 SPI Master Timing Parameters

Parameter Number	Parameter⁽¹⁾	Parameter Name	Min	Max	Unit
I1	F	Clock frequency		20	MHz
I2	T_clk	Clock period	50		ns
I3	t_LP	Clock low period		25	ns
I4	t_HT	Clock high period		25	ns
I5	D	Duty cycle	45	55	%
I6	t_IS	RX data setup time	1		ns
I7	t_IH	RX data hold time	2		ns
I8	t_OD	TX data output delay		8.5	ns
I9	t_OH	TX data hold time		8	ns

(1) Timing parameter assumes a maximum load of 20 pF.

4.1.4.1.2 SPI Slave

Figure 4-13 shows the timing diagram for the SPI slave.

Figure 4-13 SPI Slave Timing Diagram

Table 4-9 lists the timing parameters for the SPI slave.

Table 4-9 SPI Slave Timing Parameters

Parameter Number	Parameter⁽¹⁾	Parameter Name	Min	Max	Unit
I1	F	Clock frequency @ VBAT = 3.3 V		20	MHz
I1	F	Clock frequency @ VBAT ≤ 2.1 V		12	MHz
I2	Tclk	Clock period	50		ns
I3	tLP	Clock low period		25	ns
I4	tHT	Clock high period		25	ns
I5	D	Duty cycle	45	55	%
I6	tIS	RX data setup time	4		ns
I7	tIH	RX data hold time	4		ns
I8	tOD	TX data output delay		20
I9	tOH	TX data hold time		24	ns

(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.

4.1.4.2 McASP

The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A fractional divider is available for bit-clock generation.

4.1.4.2.1 I2S Transmit Mode

Figure 4-14 shows the timing diagram for the I2S transmit mode.

Figure 4-14 I2S Transmit Mode Timing Diagram

Table 4-10 lists the timing parameters for the I2S transmit mode.

Table 4-10 I2S Transmit Mode Timing Parameters

Parameter Number	Parameter⁽¹⁾	Parameter Name	Max	Unit
I1	fclk	Clock frequency	9.216	MHz
I2	tLP	Clock low period	1/2 fclk	ns
I3	tHT	Clock high period	1/2 fclk	ns
I4	tOH	TX data hold time	22	ns

(1) Timing parameter assumes a maximum load of 20 pF.

4.1.4.2.2 I2S Receive Mode

Figure 4-15 shows the timing diagram for the I2S receive mode.

Figure 4-15 I2S Receive Mode Timing Diagram

Table 4-11 lists the timing parameters for the I2S receive mode.

Table 4-11 I2S Receive Mode Timing Parameters

Parameter Number	Parameter⁽¹⁾	Parameter Name	Max	Unit
I1	fclk	Clock frequency	9.216	MHz
I2	tLP	Clock low period	1/2 fclk	ns
I3	tHT	Clock high period	1/2 fclk	ns
I4	tOH	RX data hold time	0	ns
I5	tOS	RX data setup time	15	ns

(1) Timing parameter assumes a maximum load of 20 pF.

4.1.4.3 GPIO

All digital pins of the device can be used as general-purpose input/output (GPIO) pins.The GPIO module consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24 programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable.

Figure 4-16 shows the GPIO timing diagram.

Figure 4-16 GPIO Timing

4.1.4.3.1 GPIO Output Transition Time Parameters (V_supply = 3.3 V)

Table 4-12 lists the GPIO output transition times for V_supply = 3.3 V.

Table 4-12 GPIO Output Transition Times (V_supply = 3.3 V)⁽¹⁾⁽²⁾

Drive Strength (mA)	Drive Strength Control Bits	T_r (ns)			T_f (ns)
Drive Strength (mA)	Drive Strength Control Bits	Min	Nom	Max	Min	Nom	Max
2	2MA_EN=1	8.0	9.3	10.7	8.2	9.5	11.0
	4MA_EN=0
	8MA_EN=0
4	2MA_EN=0	6.6	7.1	7.6	4.7	5.2	5.8
	4MA_EN=1
	8MA_EN=0
8	2MA_EN=0	3.2	3.5	3.7	2.3	2.6	2.9
	4MA_EN=0
	8MA_EN=1
14	2MA_EN=1	1.7	1.9	2.0	1.3	1.5	1.6
	4MA_EN=1
	8MA_EN=1

(1) V_supply = 3.3 V, T = 25°C, total pin load = 30 pF

(2) The transition data applies to the pins other than the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.

4.1.4.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.8 V)

Table 4-13 lists the GPIO output transition times for V_supply = 1.8 V.

Table 4-13 GPIO Output Transition Times (V_supply = 1.8 V)⁽¹⁾⁽²⁾

Drive Strength (mA)	Drive Strength Control Bits	T_r (ns)			T_f (ns)
Drive Strength (mA)	Drive Strength Control Bits	Min	Nom	Max	Min	Nom	Max
2	2MA_EN=1	11.7	13.9	16.3	11.5	13.9	16.7
	4MA_EN=0
	8MA_EN=0
4	2MA_EN=0	13.7	15.6	18.0	9.9	11.6	13.6
	4MA_EN=1
	8MA_EN=0
8	2MA_EN=0	5.5	6.4	7.4	3.8	4.7	5.8
	4MA_EN=0
	8MA_EN=1
14	2MA_EN=1	2.9	3.4	4.0	2.2	2.7	3.3
	4MA_EN=1
	8MA_EN=1

(1) V_supply = 1.8 V, T = 25°C, total pin load = 30 pF

(2) The transition data applies to the pins other than the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53.

4.1.4.3.3 GPIO Input Transition Time Parameters

Table 4-14 lists the input transition time parameters.

Table 4-14 GPIO Input Transition Time Parameters

Parameter	Condition	Symbol	Min	Max	Unit
Input transition time (t_r,t_f), 10% to 90%		t_r	1	3	ns
Input transition time (t_r,t_f), 10% to 90%		t_f	1	3	ns

4.1.4.4 I²C

The CC3200 microcontroller includes one I²C module operating with standard (100 Kbps) or fast (400 Kbps) transmission speeds.

Figure 4-17 shows the I²C timing diagram.

Figure 4-17 I²C Timing

Table 4-15 lists the I²C timing parameters.

Table 4-15 I²C Timing Parameters⁽³⁾

Parameter Number	Parameter	Parameter Name	Min	Max	Unit
I2	t_LP	Clock low period	See ⁽¹⁾.	-	System clock
I3	t_SRT	SCL/SDA rise time	–	See ⁽²⁾.	ns
I4	t_DH	Data hold time	NA	–
I5	t_SFT	SCL/SDA fall time	–	3	ns
I6	t_HT	Clock high time	See ⁽¹⁾.	–	System clock
I7	t_DS	Data setup time	tLP/2		System clock
I8	t_SCSR	Start condition setup time	36	–	System clock
I9	t_SCS	Stop condition setup time	24	–	System clock

(1) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal value programmed in this register.

(2) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on the external signal capacitance and external pullup register value.

(3) All timing is with 6-mA drive and 20-pF load.

4.1.4.5 IEEE 1149.1 JTAG

The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and boundary scan architecture for digital integrated circuits and provides a standardized serial interface to control the associated test logic. For detailed information on the operation of the JTAG port and TAP controller, see the IEEE Standard 1149.1,Test Access Port and Boundary- Scan Architecture.

Figure 4-18 shows the JTAG timing diagram.

Figure 4-18 JTAG Timing

Table 4-16 lists the JTAG timing parameters.

Table 4-16 JTAG Timing Parameters

Parameter Number	Parameter	Parameter Name	Min	Max	Unit
J1	fTCK	Clock frequency		15	MHz
J2	tTCK	Clock period		1/fTCK	ns
J3	tCL	Clock low period		tTCK/2	ns
J4	tCH	Clock high period		tTCK/2	ns
J7	tTMS_SU	TMS setup time	1
J8	tTMS_HO	TMS hold time	16
J9	tTDI_SU	TDI setup time	1
J10	tTDI_HO	TDI hold time	16
J11	tTDO_HO	TDO hold time		15

4.1.4.6 ADC

Table 4-17 lists the ADC electrical specifications.

Table 4-17 ADC Electrical Specifications

Parameter	Description	Condition and Assumptions	Min	Typ	Max	Unit
Nbits	Number of bits			12		Bits
INL	Integral nonlinearity	Worst-case deviation from histogram method over full scale (not including first and last three LSB levels)	–2.5		2.5	LSB
DNL	Differential nonlinearity	Worst-case deviation of any step from ideal	–1		4	LSB
Input range			0		1.4	V
Driving source impedance					100	Ω
FCLK	Clock rate	Successive approximation input clock rate		10		MHz
Input capacitance				3.2		pF
Number of channels				4
F_sample	Sampling rate of each ADC			62.5		KSPS
F_input_max	Maximum input signal frequency				31	kHz
SINAD	Signal-to-noise and distortion	Input frequency dc to 300 Hz and 1.4 V_pp sine wave input	55	60		dB
I_active	Active supply current	Average for analog-to-digital during conversion without reference current		1.5		mA
I_PD	Power-down supply current for core supply	Total for analog-to-digital when not active (this must be the SoC level test)		1		µA
Absolute offset error		FCLK = 10 MHz		±2		mV
Gain error				±2		%

Figure 4-19 shows the ADC clock timing diagram.

Figure 4-19 ADC Clock Timing

4.1.4.7 Camera Parallel Port

The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a FIFO, and generates DMA requests. The camera parallel port supports 8 bits.

Figure 4-20 shows the timing diagram for the camera parallel port.

Figure 4-20 Camera Parallel Port Timing Diagram

Table 4-18 lists the timing parameters for the camera parallel port.

Table 4-18 Camera Parallel Port Timing Parameters

Parameter Number	Parameter	Parameter Name	Max	Unit
	pCLK	Clock frequency	2	MHz
I2	T_clk	Clock period	1/pCLK	ns
I3	t_LP	Clock low period	T_clk/2	ns
I4	t_HT	Clock high period	T_clk/2	ns
I7	D	Duty cycle	45 to 55	%
I8	t_IS	RX data setup time	2	ns
I9	t_IH	RX data hold time	2	ns

4.1.4.8 UART

The CC3200 device includes two UARTs with the following features:

Programmable baud-rate generator allowing speeds up to 3 Mbps
Separate 16 x 8 TX and RX FIFOs to reduce CPU interrupt service loading
Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface
FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
Standard asynchronous communication bits for start, stop, and parity
Line-break generation and detection
Fully programmable serial interface characteristics
- 5, 6, 7, or 8 data bits
- Even, odd, stick, or no-parity bit generation and detection
- 1 or 2 stop-bit generation
RTS and CTS hardware flow support
Standard FIFO-level and End-of-Transmission interrupts
Efficient transfers using μDMA
- Separate channels for transmit and receive
- Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level
- Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level
System clock is used to generate the baud clock.

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4 Specifications

4.0.1 Absolute Maximum Ratings

4.0.2 Handling Ratings

4.0.3 Power-On Hours

4.0.4 Recommended Operating Conditions

4.0.5 Electrical Characteristics

4.0.6 WLAN Receiver Characteristics

4.0.7 WLAN Transmitter Characteristics

4.0.8 Current Consumption

4.0.9 Thermal Characteristics for RGC Package

4.1 Timing and Switching Characteristics

4.1.1 Power Supply Sequencing

4.1.2 Reset Timing

4.1.2.1 nRESET (32K XTAL)

Table 4-1 First-Time Power-Up and Reset Removal Timing Requirements (32K XTAL)

4.1.2.2 nRESET (External 32K)

Table 4-2 First-Time Power-Up and Reset Removal Timing Requirements (External 32K)

4.1.2.3 Wakeup from Hibernate

Table 4-3 Software Hibernate Timing Requirements

4.1.3 Clock Specifications

4.1.3.1 Slow Clock Using Internal Oscillator

4.1.3.2 Slow Clock Using an External Clock

4.1.3.3 Fast Clock (Fref) Using an External Crystal

4.1.3.4 Fast Clock (Fref) Using an External Oscillator

Table 4-4 External Fref Clock Requirements (–40°C to +85°C)

4.1.3.5 Input Clocks/Oscillators

Table 4-5 RTC Crystal Requirements

Table 4-6 External RTC Digital Clock Requirements

Table 4-7 WLAN Fast-Clock Crystal Requirements

4.1.4 Peripherals

4.1.4.1 SPI

4.1.4.1.1 SPI Master

Table 4-8 SPI Master Timing Parameters

4.1.4.1.2 SPI Slave

Table 4-9 SPI Slave Timing Parameters

4.1.4.2 McASP

4.1.4.2.1 I2S Transmit Mode

Table 4-10 I2S Transmit Mode Timing Parameters

4.1.4.2.2 I2S Receive Mode

Table 4-11 I2S Receive Mode Timing Parameters

4.1.4.3 GPIO

4.1.4.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)

Table 4-12 GPIO Output Transition Times (Vsupply = 3.3 V)(1)(2)

4.1.4.3.2 GPIO Output Transition Time Parameters (Vsupply = 1.8 V)

Table 4-13 GPIO Output Transition Times (Vsupply = 1.8 V)(1)(2)

4.1.4.3.3 GPIO Input Transition Time Parameters

Table 4-14 GPIO Input Transition Time Parameters

4.1.4.4 I2C

Table 4-15 I2C Timing Parameters(3)

4.1.4.5 IEEE 1149.1 JTAG

Table 4-16 JTAG Timing Parameters

4.1.4.6 ADC

Table 4-17 ADC Electrical Specifications

4.1.4.7 Camera Parallel Port

Table 4-18 Camera Parallel Port Timing Parameters

4.1.4.8 UART

4.1.3.3 Fast Clock (F_ref) Using an External Crystal

4.1.3.4 Fast Clock (F_ref) Using an External Oscillator

Table 4-4 External F_ref Clock Requirements (–40°C to +85°C)

4.1.4.3.1 GPIO Output Transition Time Parameters (V_supply = 3.3 V)

Table 4-12 GPIO Output Transition Times (V_supply = 3.3 V)⁽¹⁾⁽²⁾

Table 4-13 GPIO Output Transition Times (V_supply = 1.8 V)⁽¹⁾⁽²⁾

4.1.4.4 I²C

Table 4-15 I²C Timing Parameters⁽³⁾