ZHCSM61C November   2014  – September 2020 CC3200MOD

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3200MOD Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Pin Attributes and Pin Multiplexing
    4. 7.4 Recommended Pin Multiplexing Configurations
      1. 7.4.1 ADC Reference Accuracy Specifications
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Consumption Summary
      1. 8.5.1 Current Consumption
    6. 8.6  Brownout and Blackout Conditions
    7. 8.7  WLAN RF Characteristics
      1. 8.7.1 WLAN Receiver Characteristics
      2. 8.7.2 WLAN Transmitter Characteristics
    8. 8.8  Reset Requirement
    9. 8.9  Thermal Resistance Characteristics for MOB and MON Packages
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1 nRESET
      2. 8.10.2 Wake Up From Hibernate Timing
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Arm® Cortex®-M4 处理器内核子系统
    4. 9.4 CC3200 Device Encryption
    5. 9.5 Wi-Fi® Network Processor Subsystem
    6. 9.6 Power-Management Subsystem
      1. 9.6.1 VBAT Wide-Voltage Connection
    7. 9.7 Low-Power Operating Mode
    8. 9.8 Memory
      1. 9.8.1 External Memory Requirements
      2. 9.8.2 Internal Memory
        1. 9.8.2.1 SRAM
        2. 9.8.2.2 ROM
        3. 9.8.2.3 Memory Map
    9. 9.9 Boot Modes
      1. 9.9.1 Overview
      2. 9.9.2 Invocation Sequence and Boot Mode Selection
      3. 9.9.3 Boot Mode List
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 Reset
      3. 10.1.3 Unused Pins
      4. 10.1.4 General Layout Recommendations
      5. 10.1.5 Do's and Don'ts
    2. 10.2 Reference Schematics
    3. 10.3 Design Requirements
    4. 10.4 Detailed Design Procedure
    5. 10.5 Layout Recommendations
      1. 10.5.1 RF Section (Placement and Routing)
      2. 10.5.2 Antenna Placement and Routing
      3. 10.5.3 Transmission Line
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
      2. 12.1.2 Firmware Updates
    2. 12.2 Device Nomenclature
    3. 12.3 Documentation Support
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Drawing
    2. 13.2 Package Option
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • MOB|63
散热焊盘机械数据 (封装 | 引脚)

7.3 Pin Attributes and Pin Multiplexing

The module makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at module reset) and register control.

The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. Table 7-1 describes the general pin attributes and presents an overview of pin multiplexing. All pin multiplexing options are configurable using the pin mux registers. The following special considerations apply:

  • All I/Os support drive strengths of 2, 4, and 6 mA. Drive strength is individually configurable for each pin.
  • All I/Os support 10-μA pullup and pulldown resistors.
  • These pulls are not active and all of the I/Os remain floating while the device is in Hibernate state.
  • The VIO and VBAT supply must be tied together at all times.
  • All digital I/Os are nonfail-safe.

Table 7-1 Pin Multiplexing
GENERAL PIN ATTRIBUTES FUNCTION PAD STATES
PIN ALIAS USE SELECT AS WAKEUP SOURCE CONFIG ADDL ANALOG MUX MUXED WITH JTAG DIG. PIN MUX CONFIG REG DIG. PIN MUX CONFIG MODE VALUE SIGNAL NAME SIGNAL DESCRIPTION SIGNAL DIRECTION LPDS(1) HIB(2) nRESET = 0
GPIO10 I/O No No No GPIO_PAD_CONFIG_10
(0x4402 E0C8)		 0 GPIO10 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
1 I2C_SCL I2C Clock O
(Open Drain)		 Hi-Z
3 GT_PWM06 Pulse-Width Modulated O/P O Hi-Z
7 UART1_TX UART TX Data O 1
6 SDCARD_CLK SD Card Clock O 0
12 GT_CCP01 Timer Capture Port I Hi-Z
GPIO11 I/O Yes No No GPIO_PAD_CONFIG_11
(0x4402 E0CC)		 0 GPIO11 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
1 I2C_SDA I2C Data I/O
(Open Drain)		 Hi-Z
3 GT_PWM07 Pulse-Width Modulated O/P O Hi-Z
4 pXCLK (XVCLK) Free Clock To Parallel Camera O 0
6 SDCARD_CMD SD Card Command Line I/O Hi-Z
7 UART1_RX UART RX Data I Hi-Z
12 GT_CCP02 Timer Capture Port I Hi-Z
13 McAFSX I2S Audio Port Frame Sync O Hi-Z
GPIO12 I/O No No No GPIO_PAD_CONFIG_12
(0x4402 E0D0)		 0 GPIO12 General Purpose I/O I/O Hi-Z Hi-Z Hi-Z
3 McACLK I2S Audio Port Clock O O Hi-Z
4 pVS (VSYNC) Parallel Camera Vertical Sync I Hi-Z
5 I2C_SCL I2C Clock I/O
(Open Drain)		 Hi-Z
7 UART0_TX UART0 TX Data O 1
12 GT_CCP03 Timer Capture Port I Hi-Z
GPIO13 I/O Yes No No GPIO_PAD_CONFIG_13
(0x4402 E0D4)		 0 GPIO13 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
5 I2C_SDA I2C Data I/O
(Open Drain)
4 pHS (HSYNC) Parallel Camera Horizontal Sync I
7 UART0_RX UART0 RX Data I
12 GT_CCP04 Timer Capture Port I
GPIO14 I/O No No GPIO_PAD_CONFIG_14
(0x4402 E0D8)		 0 GPIO14 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
5 I2C_SCL I2C Clock I/O
(Open Drain)
7 GSPI_CLK General SPI Clock I/O
4 pDATA8 (CAM_D4) Parallel Camera Data Bit 4 I
12 GT_CCP05 Timer Capture Port I
GPIO15 I/O No No GPIO_PAD_CONFIG_15
(0x4402 E0DC)		 0 GPIO15 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
5 I2C_SDA I2C Data I/O
(Open Drain)
7 GSPI_MISO General SPI MISO I/O
4 pDATA9 (CAM_D5) Parallel Camera Data Bit 5 I
13 GT_CCP06 Timer Capture Port I
8 SDCARD_
DATA0		 SD Card Data I/O
GPIO16 I/O No No GPIO_PAD_CONFIG_16
(0x4402 E0E0)		 0 GPIO16 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
Hi-Z
Hi-Z
7 GSPI_MOSI General SPI MOSI I/O Hi-Z
4 pDATA10 (CAM_D6) Parallel Camera Data Bit 6 I Hi-Z
5 UART1_TX UART1 TX Data O 1
13 GT_CCP07 Timer Capture Port I Hi-Z
8 SDCARD_CLK SD Card Clock O O
GPIO17 I/O Wake-Up Source No No GPIO_PAD_CONFIG_17
(0x4402 E0E4)		 0 GPIO17 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
5 UART1_RX UART1 RX Data I
7 GSPI_CS General SPI Chip Select I/O
4 pDATA11 (CAM_D7) Parallel Camera Data Bit 7 I
8 SDCARD_
CMD		 SD Card Command Line I/O
GPIO22 I/O No No No GPIO_PAD_CONFIG_22
(0x4402 E0F8)		 0 GPIO22 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
7 McAFSX I2S Audio Port Frame Sync O Hi-Z
5 GT_CCP04 Timer Capture Port I
TDI I/O No No MUXed with JTAG TDI GPIO_PAD_CONFIG_23
(0x4402 E0FC)		 1 TDI JTAG TDI. Reset Default Pinout. I Hi-Z Hi-Z Hi-Z
0 GPIO23 General-Purpose I/O I/O
2 UART1_TX UART1 TX Data O 1
9 I2C_SCL I2C Clock I/O
(Open Drain)		 Hi-Z
TDO I/O Wake-Up Source No MUXed with JTAG TDO GPIO_PAD_CONFIG_
24
(0x4402 E100)		 1 TDO JTAG TDO. Reset Default Pinout. O Hi-Z Hi-Z Hi-Z
0 GPIO24 General-Purpose I/O I/O
5 PWM0 Pulse Width Modulated O/P O
2 UART1_RX UART1 RX Data I
9 I2C_SDA I2C Data I/O
(Open Drain)
4 GT_CCP06 Timer Capture Port I
6 McAFSX I2S Audio Port Frame Sync O
GPIO28 I/O No GPIO_PAD_CONFIG_
28
(0x4402 E110)		 0 GPIO28 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
TCK I/O No No MUXed with JTAG/SWD-TCK 1 TCK JTAG/SWD TCK Reset Default Pinout I Hi-Z Hi-Z Hi-Z
8 GT_PWM03 Pulse Width Modulated O/P O
TMS I/O No No MUXed with JTAG/SWD-TMSC GPIO_PAD_CONFIG_
29
(0x4402 E114)		 1 TMS JATG/SWD TMS Reset Default Pinout I/O Hi-Z Hi-Z Hi-Z
0 GPIO29 General-Purpose I/O
SOP2 O Only No No No GPIO_PAD_CONFIG_
25
(0x4402 E104)		 0 GPIO25 General-Purpose I/O O Hi-Z Driven Low Hi-Z
9 GT_PWM02 Pulse Width Modulated O/P O Hi-Z
2 McAFSX I2S Audio Port Frame Sync O Hi-Z
See (5) SOP2 Sense-On-Power 2 I
ANTSEL1 O Only No User config not required
(6)		 No GPIO_PAD_CONFIG_26
(0x4402 E108)		 0 ANTSEL1(3) Antenna Selection Control O Hi-Z Hi-Z Hi-Z
ANTSEL2 O Only No User config not required
(6)		 No GPIO_PAD_CONFIG_27
(0x4402 E10C)		 0 ANTSEL2(3) Antenna Selection Control O Hi-Z Hi-Z Hi-Z
SOP1 Config Sense N/A N/A N/A N/A SOP1 Sense On Power 1
SOP0 Config Sense N/A N/A N/A N/A SOP0 Sense On Power 0
GPIO0 I/O No User config not required
(6)		 No GPIO_PAD_CONFIG_0
(0x4402 E0A0)		 0 GPIO0 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
12 UART0_CTS UART0 Clear To Send Input (Active Low) I Hi-Z Hi-Z Hi-Z
6 McAXR1 I2S Audio Port Data 1 (RX or TX) I/O Hi-Z
7 GT_CCP00 Timer Capture Port I Hi-Z
9 GSPI_CS General SPI Chip Select I/O Hi-Z
10 UART1_RTS UART1 Request To Send O (Active Low) O 1
3 UART0_RTS UART0 Request To Send O (Active Low) O 1
4 McAXR0 I2S Audio Port Data 0 (RX or TX) I/O Hi-Z
GPIO30 I/O No User config not required
(6)		 No GPIO_PAD_CONFIG_30
(0x4402 E118)		 0 GPIO30 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
9 UART0_TX UART0 TX Data O 1
2 McACLK I2S Audio Port Clock O O Hi-Z
3 McAFSX I2S Audio Port Frame Sync O Hi-Z
4 GT_CCP05 Timer Capture Port I Hi-Z
7 GSPI_MISO General SPI MISO I/O Hi-Z
GPIO1 I/O No No No GPIO_PAD_CONFIG_1
(0x4402 E0A4)		 0 GPIO1 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
3 UART0_TX UART0 TX Data O 1
4 pCLK (PIXCLK) Pixel Clock From Parallel Camera Sensor I Hi-Z
6 UART1_TX UART1 TX Data O 1
7 GT_CCP01 Timer Capture Port I Hi-Z
GPIO2 Analog Input (up to 1.8 V), Digital I/O Wake-Up Source See (7) No GPIO_PAD_CONFIG_2
(0x4402 E0A8)		 See (4) ADC_CH0 ADC Channel 0 Input
(1.5-V max)		 I Hi-Z Hi-Z
0 GPIO2 General-Purpose I/O I/O Hi-Z
3 UART0_RX UART0 RX Data I Hi-Z
6 UART1_RX UART1 RX Data I Hi-Z
7 GT_CCP02 Timer Capture Port I Hi-Z
GPIO3 Analog Input (up to 1.8 V), Digital I/O No See (7) No GPIO_PAD_CONFIG_3
(0x4402 E0AC)		 See (4) ADC_CH1 ADC Channel 1 Input (1.5-V max) I Hi-Z Hi-Z
0 GPIO3 General-Purpose I/O I/O Hi-Z
6 UART1_TX UART1 TX Data O 1
4 pDATA7 (CAM_D3) Parallel Camera Data Bit 3 I Hi-Z
GPIO4 Analog Input (up to 1.8 V), Digital I/O Wake-up Source See (7) No GPIO_PAD_CONFIG_4
(0x4402 E0B0)		 See (4) ADC_CH2 ADC Channel 2 Input (1.5-V max) I Hi-Z Hi-Z
0 GPIO4 General-Purpose I/O I/O Hi-Z
6 UART1_RX UART1 RX Data I Hi-Z
4 pDATA6 (CAM_D2) Parallel Camera Data Bit 2 I Hi-Z
GPIO5 Analog Input (up to 1.8 V), Digital I/O No See (7) No GPIO_PAD_CONFIG_5
(0x4402 E0B4)		 See (4) ADC_CH3 ADC Channel 3 Input (1.5-V max) I Hi-Z Hi-Z
0 GPIO5 General-Purpose I/O I/O Hi-Z
4 pDATA5 (CAM_D1) Parallel Camera Data Bit 1 I Hi-Z
6 McAXR1 I2S Audio Port Data 1 (RX or TX) I/O Hi-Z
7 GT_CCP05 Timer Capture Port I Hi-Z
GPIO6 No No No No GPIO_PAD_CONFIG_6
(0x4402 E0B8)		 0 GPIO6 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
5 UART0_RTS UART0 Request To Send O (Active Low) O 1
4 pDATA4 (CAM_D0) Parallel Camera Data Bit 0 I Hi-Z
3 UART1_CTS UART1 Clear To Send Input (Active Low) I Hi-Z
6 UART0_CTS UART0 Clear To Send Input (Active Low) I Hi-Z
7 GT_CCP06 Timer Capture Port I Hi-Z
GPIO7 I/O No No No GPIO_PAD_CONFIG_7
(0x4402 E0BC)		 0 GPIO7 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
13 McACLKX I2S Audio Port Clock O O Hi-Z
3 UART1_RTS UART1 Request To Send O (Active Low) O 1
10 UART0_RTS UART0 Request To Send O (Active Low) O 1
11 UART0_TX UART0 TX Data O 1
GPIO8 I/O No No No GPIO_PAD_CONFIG_8
(0x4402 E0C0)		 0 GPIO8 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
6 SDCARD_IRQ Interrupt from SD Card (Future support) I
7 McAFSX I2S Audio Port Frame Sync O
12 GT_CCP06 Timer Capture Port I
GPIO9 I/O No No No GPIO_PAD_CONFIG_9
(0x4402 E0C4)		 0 GPIO9 General-Purpose I/O I/O Hi-Z Hi-Z Hi-Z
3 GT_PWM05 Pulse Width Modulated O/P O
6 SDCARD_
DATA0		 SD Cad Data I/O
7 McAXR0 I2S Audio Port Data (Rx or Tx) I/O
12 GT_CCP00 Timer Capture Port I
(1) LPDS state: The state of unused I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(2) Hibernate mode: The state of the I/Os is Hi-Z. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.
(3) To minimize leakage in some serial Flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldowns on FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.
(5) Pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the chip hardware power-up mode. For this reason, the pin must be output only when used for digital functions.
(6) Device firmware automatically enables the digital path during ROM boot.
(7) Requires user configuration to enable the analog switch of the ADC channel. (Switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |