ZHCSGZ7E March 2017 – May 2021 CC3220MOD , CC3220MODA
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
Table 7-4 describes the use, drive strength, and default state of analog- and digital-multiplexed pins at first-time power up and reset (nRESET pulled low).
| PIN | BOARD LEVEL CONFIGURATION AND USE | DEFAULT STATE AT FIRST POWER UP OR FORCED RESET | STATE AFTER CONFIGURATION OF ANALOG SWITCHES (ACTIVE, LPDS, and HIB POWER MODES) | MAXIMUM EFFECTIVE DRIVE STRENGTH (mA) |
|---|---|---|---|---|
| 25 | Connected to the enable pin of the RF switch (ANT_SEL1). Other use is not recommended. | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 26 | Connected to the enable pin of the RF switch (ANT_SEL2). Other use is not recommended. | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 44 | Generic I/O | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 42 | Generic I/O | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 47 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 48 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 49 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 50 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |