米6体育平台手机版

ZHCSJ35C September 2016 – May 2021 CC3220R , CC3220S , CC3220SF

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RGK|64
- MPQF273C

散热焊盘机械数据 (封装 | 引脚)

RGK|64
- QFND565B

订购信息

7.2.1 Pin Descriptions

PINS		TYPE	DESCRIPTION	SELECT AS WAKEUP SOURCE	CONFIGURE ADDITIONAL ANALOG MUX	MUXED WITH JTAG
NO.	NAME	TYPE	DESCRIPTION	SELECT AS WAKEUP SOURCE	CONFIGURE ADDITIONAL ANALOG MUX	MUXED WITH JTAG
1	GPIO10	I/O	General-purpose input or output	No	No	No
2	GPIO11	I/O	General-purpose input or output	Yes	No	No
3	GPIO12	I/O	General-purpose input or output	No	No	No
4	GPIO13	I/O	General-purpose input or output	Yes	No	No
5	GPIO14	I/O	General-purpose input or output	No	No	No
6	GPIO15	I/O	General-purpose input or output	No	No	No
7	GPIO16	I/O	General-purpose input or output	No	No	No
8	GPIO17	I/O	General-purpose input or output	Yes	No	No
9	VDD_DIG1	Power	Internal digital core voltage	N/A	N/A	N/A
10	VIN_IO1	Power	I/O power supply (same as battery voltage)	N/A	N/A	N/A
11	FLASH_SPI_CLK	O	Serial flash interface: SPI clock	N/A	N/A	N/A
12	FLASH_SPI_DOUT	O	Serial flash interface: SPI data out	N/A	N/A	N/A
13	FLASH_SPI_DIN	I	Serial flash interface: SPI data in	N/A	N/A	N/A
14	FLASH_SPI_CS	O	Serial flash interface: SPI chip select	N/A	N/A	N/A
15	GPIO22	I/O	General-purpose input or output	No	No	No
16	TDI	I/O	JTAG interface: data input	No	No	Muxed with JTAG TDI
17	TDO	I/O	JTAG interface: data output	Yes	No	Muxed with JTAG TDO
18	GPIO28	I/O	General-purpose input or output	No	No	No
19	TCK	I/O	JTAG/SWD interface: clock	No	No	Muxed with JTAG/ SWD-TCK
20	TMS	I/O	JTAG/SWD interface: mode select or SWDIO	No	No	Muxed with JTAG/ SWD-TMSC
21⁽²⁾	SOP2	I	Configuration sense-on-power 2	No	No	No
22	WLAN_XTAL_N	Analog	40-MHz crystal. Pulldown if external TCXO is used.	N/A	N/A	N/A
23	WLAN_XTAL_P	Analog	40-MHz crystal or TCXO clock input	N/A	N/A	N/A
24	VDD_PLL	Power	Internal analog voltage	N/A	N/A	N/A
25	LDO_IN2	Power	Internal analog RF supply from analog DC/DC output	N/A	N/A	N/A
26	NC	—	No connect	N/A	N/A	N/A
27	NC	—	Reserved	N/A	N/A	N/A
28	NC	—	Reserved	N/A	N/A	N/A
29⁽¹⁾	ANTSEL1	O	Antenna selection control	No	User configuration not required ⁽³⁾	No
30⁽¹⁾	ANTSEL2	O	Antenna selection control	No	User configuration not required ⁽³⁾	No
31	RF_BG	RF	RF BG band: 2.4-GHz TX, RX	N/A	N/A	N/A
32	nRESET	I	Master chip reset input. Active low input.	N/A	N/A	N/A
33	VDD_PA_IN	Power	Internal RF power amplifier (PA) input from PA DC/DC output	N/A	N/A	N/A
34	SOP1	I	Configuration sense-on-power 1	N/A	N/A	N/A
35	SOP0	I	Configuration sense-on-power 0	N/A	N/A	N/A
36	LDO_IN1	Power	Internal Analog RF supply from analog DC/DC output	N/A	N/A	N/A
37	VIN_DCDC_ANA		Analog DC/DC supply input (same as battery voltage [V_BAT])	N/A	N/A	N/A
38	DCDC_ANA_SW	Power	Internal Analog DC/DC converter switching node	N/A	N/A	N/A
39	VIN_DCDC_PA	Power	PA DC/DC converter input supply (same as battery voltage [V_BAT])	N/A	N/A	N/A
40	DCDC_PA_SW_P	Power	Internal PA DC/DC converter +ve switching node	N/A	N/A	N/A
41	DCDC_PA_SW_N	Power	Internal PA DC/DC converter –ve switching node	N/A	N/A	N/A
42	DCDC_PA_OUT	Power	Internal PA buck DC/DC converter output	N/A	N/A	N/A
43	DCDC_DIG_SW	Power	Internal Digital DC/DC converter switching node	N/A	N/A	N/A
44	VIN_DCDC_DIG	Power	Digital DC/DC converter supply input (same as battery voltage [V_BAT])	N/A	N/A	N/A
45⁽⁴⁾	DCDC_ANA2_SW_P	I/O	Analog2 DC/DC converter +ve switching node	No	User configuration not required ⁽³⁾	No
46	DCDC_ANA2_SW_N	Power	Internal Analog2 DC/DC converter –ve switching node	N/A	N/A	N/A
47	VDD_ANA2	Power	Internal Analog2 DC/DC output	N/A	N/A	N/A
48	VDD_ANA1	Power	Internal Analog1 power supply fed by analog2 DC/DC converter output	N/A	N/A	N/A
49	VDD_RAM	Power	Internal SRAM LDO output	N/A	N/A	N/A
50	GPIO0	I/O	General-purpose input or output	No	User configuration not required ⁽³⁾	No
51	RTC_XTAL_P	Analog	32.768-kHz XTAL_P or external CMOS level clock input	N/A	N/A	N/A
52⁽⁵⁾	RTC_XTAL_N	Analog	32.768-kHz XTAL_N	N/A	User configuration not required ⁽³⁾⁽⁷⁾	No
53	GPIO30	I/O	General-purpose input or output	No	User configuration not required ⁽³⁾	No
54	VIN_IO2	Power	device supply voltage (V_BAT)	N/A	N/A	N/A
55	GPIO1	I/O	General-purpose input or output	No	No	No
56	VDD_DIG2	Power	internal digital core voltage	N/A	N/A	N/A
57⁽⁶⁾	GPIO2	I/O	Analog input (up to 1.5-V ) or general-purpose input or output	Yes	See ⁽⁸⁾	No
58⁽⁶⁾	GPIO3	I/O	Analog input (up to 1.5-V ) or general-purpose input or output	No	See ⁽⁸⁾	No
59⁽⁶⁾	GPIO4	I/O	Analog input (up to 1.5-V ) or general-purpose input or output	Yes	See ⁽⁸⁾	No
60⁽⁶⁾	GPIO5	I/O	Analog input (up to 1.5 V) or general-purpose input or output	No	See ⁽⁸⁾	No
61	GPIO6	I/O	General-purpose input or output	No	No	No
62	GPIO7	I/O	General-purpose input or output	No	No	No
63	GPIO8	I/O	General-purpose input or output	No	No	No
64	GPIO9	I/O	General-purpose input or output	No	No	No
GND_TAB		—	Thermal pad and electrical ground	N/A	N/A	N/A

(1) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities.

(2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(3) Device firmware automatically enables the digital path during ROM boot.

(4) Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

(5) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.

(6) This pin is shared by the ADC inputs and digital I/O pad cells.

(7) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor.

(8) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.

Table 7-1 Pin Attributes

PIN NO.	SIGNAL NAME⁽¹⁾	SIGNAL TYPE⁽²⁾	PIN MUX ENCODING	SIGNAL DIRECTION	PAD STATES
PIN NO.	SIGNAL NAME⁽¹⁾	SIGNAL TYPE⁽²⁾	PIN MUX ENCODING	SIGNAL DIRECTION	LPDS⁽³⁾	Hib⁽⁴⁾	nRESET = 0
1	GPIO10 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	I2C_SCL		1	I/O (open drain)	Hi-Z, Pull, Drive
	GT_PWM06		3	O	Hi-Z, Pull, Drive
	UART1_TX		7	O	1
	SDCARD_CLK		6	O	0
	GT_CCP01		12	I	Hi-Z, Pull, Drive
2	GPIO11 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	I2C_SDA		1	I/O (open drain)	Hi-Z, Pull, Drive
	GT_PWM07		3	O	Hi-Z, Pull, Drive
	pXCLK (XVCLK)		4	O	0
	SDCARD_CMD		6	I/O (open drain)	Hi-Z, Pull, Drive
	UART1_RX		7	I	Hi-Z, Pull, Drive
	GT_CCP02		12	I	Hi-Z, Pull, Drive
	McAFSX		13	O	Hi-Z, Pull, Drive
3	GPIO12 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	McACLK		3	O	Hi-Z, Pull, Drive
	pVS (VSYNC)		4	I	Hi-Z, Pull, Drive
	I2C_SCL		5	I/O (open drain)	Hi-Z, Pull, Drive
	UART0_TX		7	O	1
	GT_CCP03		12	I	Hi-Z, Pull, Drive
4	GPIO13 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	I2C_SDA		5	I/O (open drain)
	pHS (HSYNC)		4	I
	UART0_RX		7	I
	GT_CCP04		12	I
5	GPIO14 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	I2C_SCL		5	I/O (open drain)
	GSPI_CLK		7	I/O
	pDATA8 (CAM_D4)		4	I
	GT_CCP05		12	I
6	GPIO15 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	I2C_SDA		5	I/O (open drain)
	GSPI_MISO		7	I/O
	pDATA9 (CAM_D5)		4	I
	GT_CCP06		13	I
	SDCARD_DATA0		8	I/O
7	GPIO16 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GSPI_MOSI		7	I/O	Hi-Z, Pull, Drive
	pDATA10 (CAM_D6)		4	I	Hi-Z, Pull, Drive
	UART1_TX		5	O	1
	GT_CCP07		13	I	Hi-Z, Pull, Drive
	SDCARD_CLK		8	O	0
8	GPIO17 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	UART1_RX		5	I
	GSPI_CS		7	I/O
	pDATA11 (CAM_D7)		4	I
	SDCARD_CMD		8	I/O
9	VDD_DIG1 (PN)	—	N/A	N/A	N/A	N/A	N/A
10	VIN_IO1	—	N/A	N/A	N/A	N/A	N/A
11	FLASH_SPI_CLK	O	N/A	O	Hi-Z, Pull, Drive⁽⁵⁾	Hi-Z, Pull, Drive	Hi-Z
12	FLASH_SPI_DOUT	O	N/A	O	Hi-Z, Pull, Drive⁽⁵⁾	Hi-Z, Pull, Drive	Hi-Z
13	FLASH_SPI_DIN	I	N/A	I	Hi-Z, Pull, Drive⁽⁵⁾	Hi-Z	Hi-Z
14	FLASH_SPI_CS	O	N/A	O	1	Hi-Z, Pull, Drive	Hi-Z
15	GPIO22 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	McAFSX	O	7	O
	GT_CCP04	I	5	I
16	TDI (PN)	I/O	1	I	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GPIO23		0	I/O	Hi-Z, Pull, Drive
	UART1_TX		2	O	1
	I2C_SCL		9	I/O (open drain)	Hi-Z, Pull, Drive
17	TDO (PN)	I/O	1	O	Hi-Z, Pull, Drive	Driven high in SWD; driven low in 4-wire JTAG	Hi-Z
	GPIO24		0	I/O
	PWM0		5	O
	UART1_RX		2	I
	I2C_SDA		9	I/O (open drain)
	GT_CCP06		4	I
	McAFSX		6	O
18	GPIO28	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
19	TCK (PN)	I/O	1	I	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
19	GT_PWM03	I/O	8	O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
20	TMS (PN)	I/O	1	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
20	GPIO29	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
21⁽⁶⁾	GPIO25	O	0	O	Hi-Z, Pull, Drive	Driven low	Hi-Z
	GT_PWM02		9	O	Hi-Z, Pull, Drive
	McAFSX		2	O	Hi-Z, Pull, Drive
	TCXO_EN		N/A (see ⁽⁸⁾)	O	0
	SOP2 (PN)		N/A (see ⁽⁹⁾)	I	Hi-Z, Pull, Drive
22	WLAN_XTAL_N	—	N/A (see ⁽⁸⁾)	N/A	N/A	N/A	N/A
23	WLAN_XTAL_P	—	N/A	N/A	N/A	N/A	N/A
24	VDD_PLL	—	N/A	N/A	N/A	N/A	N/A
25	LDO_IN2	—	N/A	N/A	N/A	N/A	N/A
26	NC	—	N/A	N/A	N/A	N/A	N/A
27	NC	—	N/A	N/A	N/A	N/A	N/A
28	NC	—	N/A	N/A	N/A	N/A	N/A
29⁽¹⁰⁾	ANTSEL1	O	0	O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
30⁽¹⁰⁾	ANTSEL2	O	0	O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
31	RF_BG	—	N/A	N/A	N/A	N/A	N/A
32	nRESET	—	N/A	N/A	N/A	N/A	N/A
33	VDD_PA_IN	—	N/A	N/A	N/A	N/A	N/A
34	SOP1	—	N/A	N/A	N/A	N/A	N/A
35	SOP0	—	N/A	N/A	N/A	N/A	N/A
36	LDO_IN1	—	N/A	N/A	N/A	N/A	N/A
37	VIN_DCDC_ANA	—	N/A	N/A	N/A	N/A	N/A
38	DCDC_ANA_SW	—	N/A	N/A	N/A	N/A	N/A
39	VIN_DCDC_PA	—	N/A	N/A	N/A	N/A	N/A
40	DCDC_PA_SW_P	—	N/A	N/A	N/A	N/A	N/A
41	DCDC_PA_SW_N	—	N/A	N/A	N/A	N/A	N/A
42	DCDC_PA_OUT	—	N/A	N/A	N/A	N/A	N/A
43	DCDC_DIG_SW	—	N/A	N/A	N/A	N/A	N/A
44	VIN_DCDC_DIG	—	N/A	N/A	N/A	N/A	N/A
45⁽⁷⁾	GPIO31	I/O	0	I/O	Hi-Z	Hi-Z	Hi-Z
	UART0_RX		9	I
	McAFSX		12	O
	UART1_RX		2	I
	McAXR0		6	I/O
	GSPI_CLK		7	I/O
	DCDC_ANA2_SW_P (PN)	—	N/A (see ⁽⁸⁾)	N/A	N/A	N/A	N/A
46	DCDC_ANA2_SW_N	—	N/A	N/A	N/A	N/A	N/A
47	VDD_ANA2	—	N/A	N/A	N/A	N/A	N/A
48	VDD_ANA1	—	N/A	N/A	N/A	N/A	N/A
49	VDD_RAM	—	N/A	N/A	N/A	N/A	N/A
50	GPIO0 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	UART0_CTS		12	I	Hi-Z, Pull, Drive
	McAXR1		6	I/O	Hi-Z, Pull, Drive
	GT_CCP00		7	I	Hi-Z, Pull, Drive
	GSPI_CS		9	I/O	Hi-Z, Pull, Drive
	UART1_RTS		10	O	1
	UART0_RTS		3	O	1
	McAXR0		4	I/O	Hi-Z, Pull, Drive
51	RTC_XTAL_P	—	N/A	N/A	N/A	N/A	N/A
52⁽¹¹⁾	RTC_XTAL_N (PN)	O	N/A	N/A	N/A	Hi-Z, Pull, Drive	Hi-Z
	GPIO32		0	O	Hi-Z, Pull, Drive
	McACLK		2	O
	McAXR0		4	O
	UART0_RTS		6	O	1
	GSPI_MOSI		8	O	Hi-Z, Pull, Drive
53	GPIO30 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	UART0_TX		9	O	1
	McACLK		2	O	Hi-Z, Pull, Drive
	McAFSX		3	O
	GT_CCP05		4	I
	GSPI_MISO		7	I/O
54	VIN_IO2	—	N/A	N/A	N/A	N/A	N/A
55	GPIO1 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	UART0_TX		3	O	1
	pCLK (PIXCLK)		4	I	Hi-Z, Pull, Drive
	UART1_TX		6	O	1
	GT_CCP01		7	I	Hi-Z, Pull, Drive
56	VDD_DIG2	—	N/A	N/A	N/A	N/A	N/A
57⁽¹²⁾	ADC_CH0	Analog input (up to 1.5 V) or digital I/O	N/A (see ⁽⁸⁾)	I	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GPIO2 (PN)		0	I/O
	UART0_RX		3	I
	UART1_RX		6	I
	GT_CCP02		7	I
58⁽¹²⁾	ADC_CH1	Analog input (up to 1.5 V) or digital I/O	N/A (see ⁽⁸⁾)	I	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GPIO3 (PN)		0	I/O	Hi-Z, Pull, Drive
	UART1_TX		6	O	1
	pDATA7 (CAM_D3)		4	I	Hi-Z, Pull, Drive
59⁽¹²⁾	ADC_CH2	Analog input (up to 1.5 V) or digital I/O	N/A (see ⁽⁸⁾)	I	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GPIO4 (PN)		0	I/O
	UART1_RX		6	I
	pDATA6 (CAM_D2)		4	I
60⁽¹²⁾	ADC_CH3	Analog input (up to 1.5 V) or digital I/O	N/A (see ⁽⁸⁾)	I	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GPIO5 (PN)		0	I/O
	pDATA5 (CAM_D1)		4	I
	McAXR1		6	I/O
	GT_CCP05		7	I
61	GPIO6 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	UART0_RTS		5	O	1
	pDATA4 (CAM_D0)		4	I	Hi-Z, Pull, Drive
	UART1_CTS		3	I
	UART0_CTS		6	I
	GT_CCP06		7	I
62	GPIO7 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	McACLKX		13	O	Hi-Z, Pull, Drive
	UART1_RTS		3	O	1
	UART0_RTS		10	O
	UART0_TX		11	O
63	GPIO8 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	SDCARD_IRQ		6	I
	McAFSX		7	O
	GT_CCP06		12	I
64	GPIO9 (PN)	I/O	0	I/O	Hi-Z, Pull, Drive	Hi-Z, Pull, Drive	Hi-Z
	GT_PWM05		3	O
	SDCARD_DATA0		6	I/O
	McAXR0		7	I/O
	GT_CCP00		12	I
GND_TAB		—	N/A	N/A	N/A	N/A	N/A

(1) Signals names with (PN) denote the default pin name.

(2) Signal Types: I = Input, O = Output, I/O = Input or Output.

(3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.

(4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need.

(5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins.

(6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(7) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

(8) For details on proper use, see Section 7.5.

(9) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode. For this reason, the pin must be output only when used for digital functions.

(10) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities.

(11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions.

(12) This pin is shared by the ADC inputs and digital I/O pad cells.

Note:

The ADC inputs are tolerant up to 1.8 V (see Section 8.14.6.6.1 for more details about the usable range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For more information about drive strength and reset states for analog-digital multiplexed pins, see Section 7.5.